idt71321.vhd

vhdl cod for ram.For sp3e

--------------------------------------------------------------------------------
--  File Name: idt71321.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2005 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY :
--
--  version:   | author:     | mod date:     | changes made:
--  V1.0        N.Makljenovic  05 Feb 17       Initial release
--
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
--
--  Library:    RAM
--  Technology: CMOS
--  Part:       idt71321
--
--  Description: Dual Port RAM 2K x 8 master
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
                USE STD.textio.ALL;

LIBRARY FMF;    USE FMF.gen_utils.all;
                USE FMF.conversions.all;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY idt71321 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_IOR7                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR6                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR5                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR4                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR3                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR2                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR1                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR0                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL7                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL6                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL5                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL4                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL3                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL2                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL1                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL0                : VitalDelayType01 := VitalZeroDelay01;
        tipd_OERNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_OELNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_RWR                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_RWL                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_CERNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_CELNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR0                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR1                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR2                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR3                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR4                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR5                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR6                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR7                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR8                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR9                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR10                : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL0                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL1                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL2                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL3                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL4                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL5                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL6                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL7                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL8                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL9                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL10                : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_AL0_IOL0             : VitalDelayType01 := UnitDelay01;
        tpd_OELNeg_IOL0          : VitalDelayType01Z := UnitDelay01Z;
        tpd_CELNeg_IOL0          : VitalDelayType01Z := UnitDelay01Z;
        tpd_RWL_INTRNeg          : VitalDelayType01Z := UnitDelay01Z;
        tpd_CELNeg_BUSYLNeg      : VitalDelayType01Z := UnitDelay01Z;
        tpd_RWL_IOL0             : VitalDelayType01Z := UnitDelay01Z;

        -- tsetup values: setup times
        tsetup_AL0_AR0          : VitalDelayType    := UnitDelay;
        tsetup_AL0_OELNeg       : VitalDelayType    := UnitDelay;
        tsetup_AL0_CELNeg       : VitalDelayType    := UnitDelay;
        tsetup_AL0_RWL          : VitalDelayType    := UnitDelay;
        tsetup_CELNeg_RWL       : VitalDelayType    := UnitDelay;
        tsetup_IOL0_RWL         : VitalDelayType    := UnitDelay;
        -- thold values: hold times
        thold_IOL0_RWL           : VitalDelayType    := UnitDelay;
        thold_RWL_BUSYLNeg       : VitalDelayType    := UnitDelay;
        thold_AL0_CELNeg         : VitalDelayType    := UnitDelay;
        -- pulse width
        tpw_RWL_negedge          : VitalDelayType    := UnitDelay;
        tpw_AL0_negedge          : VitalDelayType    := UnitDelay;
        tpw_AL0_posedge          : VitalDelayType    := UnitDelay;
        -- tdevice values: values for internal delays
        tdevice_TWDD              : VitalDelayType    := UnitDelay;
        tdevice_TDDD              : VitalDelayType    := UnitDelay;
        tdevice_TBDD              : VitalDelayType    := UnitDelay;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        -- memory file to be loaded
        mem_file_name       : STRING    := "none";
        UserPreload         : BOOLEAN   := FALSE;
        InterruptEnable     : BOOLEAN   := FALSE;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        IOR7            : INOUT std_ulogic := 'U';
        IOR6            : INOUT std_ulogic := 'U';
        IOR5            : INOUT std_ulogic := 'U';
        IOR4            : INOUT std_ulogic := 'U';
        IOR3            : INOUT std_ulogic := 'U';
        IOR2            : INOUT std_ulogic := 'U';
        IOR1            : INOUT std_ulogic := 'U';
        IOR0            : INOUT std_ulogic := 'U';
        IOL7            : INOUT std_ulogic := 'U';
        IOL6            : INOUT std_ulogic := 'U';
        IOL5            : INOUT std_ulogic := 'U';
        IOL4            : INOUT std_ulogic := 'U';
        IOL3            : INOUT std_ulogic := 'U';
        IOL2            : INOUT std_ulogic := 'U';
        IOL1            : INOUT std_ulogic := 'U';
        IOL0            : INOUT std_ulogic := 'U';
        OERNeg          : IN    std_ulogic := 'U';
        OELNeg          : IN    std_ulogic := 'U';
        RWR             : IN    std_ulogic := 'U';
        RWL             : IN    std_ulogic := 'U';
        CERNeg          : IN    std_ulogic := 'U';
        CELNeg          : IN    std_ulogic := 'U';
        BUSYLNeg        : OUT   std_ulogic := 'U';
        BUSYRNeg        : OUT   std_ulogic := 'U';
        INTLNeg         : OUT   std_ulogic := 'U';
        INTRNeg         : OUT   std_ulogic := 'U';
        AR0             : IN    std_ulogic := 'U';
        AR1             : IN    std_ulogic := 'U';
        AR2             : IN    std_ulogic := 'U';
        AR3             : IN    std_ulogic := 'U';
        AR4             : IN    std_ulogic := 'U';
        AR5             : IN    std_ulogic := 'U';
        AR6             : IN    std_ulogic := 'U';
        AR7             : IN    std_ulogic := 'U';
        AR8             : IN    std_ulogic := 'U';
        AR9             : IN    std_ulogic := 'U';
        AR10            : IN    std_ulogic := 'U';
        AL0             : IN    std_ulogic := 'U';
        AL1             : IN    std_ulogic := 'U';
        AL2             : IN    std_ulogic := 'U';
        AL3             : IN    std_ulogic := 'U';
        AL4             : IN    std_ulogic := 'U';
        AL5             : IN    std_ulogic := 'U';
        AL6             : IN    std_ulogic := 'U';
        AL7             : IN    std_ulogic := 'U';
        AL8             : IN    std_ulogic := 'U';
        AL9             : IN    std_ulogic := 'U';
        AL10            : IN    std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of idt71321 : ENTITY IS TRUE;
END idt71321;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of idt71321 IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT partID         : STRING := "idt71321";
    CONSTANT MaxData        : NATURAL := 16#FF#;
    CONSTANT TotalLOC       : NATURAL := 2047;
    CONSTANT HiAbit         : NATURAL := 10;
    CONSTANT HiDbit         : NATURAL := 7;
    CONSTANT DataWidth      : NATURAL := 8;

    SIGNAL IOR7_ipd         : std_ulogic := 'U';
    SIGNAL IOR6_ipd         : std_ulogic := 'U';
    SIGNAL IOR5_ipd         : std_ulogic := 'U';
    SIGNAL IOR4_ipd         : std_ulogic := 'U';
    SIGNAL IOR3_ipd         : std_ulogic := 'U';
    SIGNAL IOR2_ipd         : std_ulogic := 'U';
    SIGNAL IOR1_ipd         : std_ulogic := 'U';
    SIGNAL IOR0_ipd         : std_ulogic := 'U';
    SIGNAL IOL7_ipd         : std_ulogic := 'U';
    SIGNAL IOL6_ipd         : std_ulogic := 'U';
    SIGNAL IOL5_ipd         : std_ulogic := 'U';
    SIGNAL IOL4_ipd         : std_ulogic := 'U';
    SIGNAL IOL3_ipd         : std_ulogic := 'U';
    SIGNAL IOL2_ipd         : std_ulogic := 'U';
    SIGNAL IOL1_ipd         : std_ulogic := 'U';
    SIGNAL IOL0_ipd         : std_ulogic := 'U';
    SIGNAL OERNeg_ipd       : std_ulogic := 'U';
    SIGNAL OELNeg_ipd       : std_ulogic := 'U';
    SIGNAL RWR_ipd          : std_ulogic := 'U';
    SIGNAL RWL_ipd          : std_ulogic := 'U';
    SIGNAL CERNeg_ipd       : std_ulogic := 'U';
    SIGNAL CELNeg_ipd       : std_ulogic := 'U';
    SIGNAL AR0_ipd          : std_ulogic := 'U';
    SIGNAL AR1_ipd          : std_ulogic := 'U';
    SIGNAL AR2_ipd          : std_ulogic := 'U';
    SIGNAL AR3_ipd          : std_ulogic := 'U';
    SIGNAL AR4_ipd          : std_ulogic := 'U';
    SIGNAL AR5_ipd          : std_ulogic := 'U';
    SIGNAL AR6_ipd          : std_ulogic := 'U';
    SIGNAL AR7_ipd          : std_ulogic := 'U';
    SIGNAL AR8_ipd          : std_ulogic := 'U';
    SIGNAL AR9_ipd          : std_ulogic := 'U';
    SIGNAL AR10_ipd         : std_ulogic := 'U';
    SIGNAL AL0_ipd          : std_ulogic := 'U';
    SIGNAL AL1_ipd          : std_ulogic := 'U';
    SIGNAL AL2_ipd          : std_ulogic := 'U';
    SIGNAL AL3_ipd          : std_ulogic := 'U';
    SIGNAL AL4_ipd          : std_ulogic := 'U';
    SIGNAL AL5_ipd          : std_ulogic := 'U';
    SIGNAL AL6_ipd          : std_ulogic := 'U';
    SIGNAL AL7_ipd          : std_ulogic := 'U';
    SIGNAL AL8_ipd          : std_ulogic := 'U';
    SIGNAL AL9_ipd          : std_ulogic := 'U';
    SIGNAL AL10_ipd         : std_ulogic := 'U';

    SIGNAL TWDD_in       : std_ulogic := '0';
    SIGNAL TWDD_out      : std_ulogic := '0';
    SIGNAL TDDD_in       : std_ulogic := '0';
    SIGNAL TDDD_out      : std_ulogic := '0';
    SIGNAL TBDD_in       : std_ulogic := '0';
    SIGNAL TBDD_out      : std_ulogic := '0';
BEGIN
    ---------------------------------------------------------------------------
    -- Internal Delays
    ---------------------------------------------------------------------------
    -- Artificial VITAL primitives to incorporate internal delays

    TWDD :VitalBuf(TWDD_out, TWDD_in,  (tdevice_TWDD  ,UnitDelay));
    TDDD :VitalBuf(TDDD_out, TDDD_in,  (tdevice_TDDD  ,UnitDelay));
    TBDD :VitalBuf(TBDD_out, TBDD_in,  (tdevice_TBDD  ,UnitDelay));

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN
        w_0 : VitalWireDelay (RWR_ipd, RWR, tipd_RWR);
        w_1 : VitalWireDelay (RWL_ipd, RWL, tipd_RWL);
        w_2 : VitalWireDelay (CERNeg_ipd, CERNeg, tipd_CERNeg);
        w_3 : VitalWireDelay (CELNeg_ipd, CELNeg, tipd_CELNeg);
        w_4 : VitalWireDelay (OERNeg_ipd, OERNeg, tipd_OERNeg);
        w_6 : VitalWireDelay (OELNeg_ipd, OELNeg, tipd_OELNeg);
        w_7 : VitalWireDelay (AR0_ipd, AR0, tipd_AR0);
        w_8 : VitalWireDelay (AR1_ipd, AR1, tipd_AR1);
        w_9  : VitalWireDelay (AR2_ipd, AR2, tipd_AR2);
        w_10 : VitalWireDelay (AR3_ipd, AR3, tipd_AR3);
        w_11 : VitalWireDelay (AR4_ipd, AR4, tipd_AR4);
        w_12 : VitalWireDelay (AR5_ipd, AR5, tipd_AR5);
        w_13 : VitalWireDelay (AR6_ipd, AR6, tipd_AR6);
        w_14 : VitalWireDelay (AR7_ipd, AR7, tipd_AR7);
        w_15 : VitalWireDelay (AR8_ipd, AR8, tipd_AR8);
        w_16 : VitalWireDelay (AR9_ipd, AR9, tipd_AR9);
        w_17 : VitalWireDelay (AR10_ipd, AR10, tipd_AR10);
        w_18 : VitalWireDelay (AL0_ipd, AL0, tipd_AL0);
        w_19 : VitalWireDelay (AL1_ipd, AL1, tipd_AL1);
        w_20 : VitalWireDelay (AL2_ipd, AL2, tipd_AL2);
        w_21 : VitalWireDelay (AL3_ipd, AL3, tipd_AL3);
        w_22 : VitalWireDelay (AL4_ipd, AL4, tipd_AL4);
        w_23 : VitalWireDelay (AL5_ipd, AL5, tipd_AL5);
        w_24 : VitalWireDelay (AL6_ipd, AL6, tipd_AL6);
        w_25 : VitalWireDelay (AL7_ipd, AL7, tipd_AL7);
        w_26 : VitalWireDelay (AL8_ipd, AL8, tipd_AL8);
        w_27 : VitalWireDelay (AL9_ipd, AL9, tipd_AL9);
        w_28 : VitalWireDelay (AL10_ipd, AL10, tipd_AL10);
        w_29 : VitalWireDelay (IOR7_ipd, IOR7, tipd_IOR7);
        w_30 : VitalWireDelay (IOR6_ipd, IOR6, tipd_IOR6);
        w_31 : VitalWireDelay (IOR5_ipd, IOR5, tipd_IOR5);
        w_32 : VitalWireDelay (IOR4_ipd, IOR4, tipd_IOR4);
        w_33 : VitalWireDelay (IOR3_ipd, IOR3, tipd_IOR3);
        w_34 : VitalWireDelay (IOR2_ipd, IOR2, tipd_IOR2);
        w_35 : VitalWireDelay (IOR1_ipd, IOR1, tipd_IOR1);
        w_36 : VitalWireDelay (IOR0_ipd, IOR0, tipd_IOR0);
        w_37 : VitalWireDelay (IOL7_ipd, IOL7, tipd_IOL7);
        w_38 : VitalWireDelay (IOL6_ipd, IOL6, tipd_IOL6);
        w_39 : VitalWireDelay (IOL5_ipd, IOL5, tipd_IOL5);
        w_40 : VitalWireDelay (IOL4_ipd, IOL4, tipd_IOL4);
        w_41 : VitalWireDelay (IOL3_ipd, IOL3, tipd_IOL3);
        w_42 : VitalWireDelay (IOL2_ipd, IOL2, tipd_IOL2);
        w_43 : VitalWireDelay (IOL1_ipd, IOL1, tipd_IOL1);
        w_44 : VitalWireDelay (IOL0_ipd, IOL0, tipd_IOL0);
    END BLOCK;

    ----------------------------------------------------------------------------
    -- Main Behavior Block
    ----------------------------------------------------------------------------
    Behavior: BLOCK

        PORT (
            ALIn         : IN    std_logic_vector(HiAbit downto 0);
            ARIn         : IN    std_logic_vector(HiAbit downto 0);