k7r323682m.vhd

vhdl cod for ram.For sp3e

    SIGNAL A6_ipd              : std_ulogic := 'U';
    SIGNAL A7_ipd              : std_ulogic := 'U';
    SIGNAL A8_ipd              : std_ulogic := 'U';
    SIGNAL A9_ipd              : std_ulogic := 'U';
    SIGNAL A10_ipd             : std_ulogic := 'U';
    SIGNAL A11_ipd             : std_ulogic := 'U';
    SIGNAL A12_ipd             : std_ulogic := 'U';
    SIGNAL A13_ipd             : std_ulogic := 'U';
    SIGNAL A14_ipd             : std_ulogic := 'U';
    SIGNAL A15_ipd             : std_ulogic := 'U';
    SIGNAL A16_ipd             : std_ulogic := 'U';
    SIGNAL A17_ipd             : std_ulogic := 'U';
    SIGNAL A18_ipd             : std_ulogic := 'U';
    SIGNAL D0_ipd              : std_ulogic := 'U';
    SIGNAL D1_ipd              : std_ulogic := 'U';
    SIGNAL D2_ipd              : std_ulogic := 'U';
    SIGNAL D3_ipd              : std_ulogic := 'U';
    SIGNAL D4_ipd              : std_ulogic := 'U';
    SIGNAL D5_ipd              : std_ulogic := 'U';
    SIGNAL D6_ipd              : std_ulogic := 'U';
    SIGNAL D7_ipd              : std_ulogic := 'U';
    SIGNAL D8_ipd              : std_ulogic := 'U';
    SIGNAL D9_ipd              : std_ulogic := 'U';
    SIGNAL D10_ipd             : std_ulogic := 'U';
    SIGNAL D11_ipd             : std_ulogic := 'U';
    SIGNAL D12_ipd             : std_ulogic := 'U';
    SIGNAL D13_ipd             : std_ulogic := 'U';
    SIGNAL D14_ipd             : std_ulogic := 'U';
    SIGNAL D15_ipd             : std_ulogic := 'U';
    SIGNAL D16_ipd             : std_ulogic := 'U';
    SIGNAL D17_ipd             : std_ulogic := 'U';
    SIGNAL D18_ipd             : std_ulogic := 'U';
    SIGNAL D19_ipd             : std_ulogic := 'U';
    SIGNAL D20_ipd             : std_ulogic := 'U';
    SIGNAL D21_ipd             : std_ulogic := 'U';
    SIGNAL D22_ipd             : std_ulogic := 'U';
    SIGNAL D23_ipd             : std_ulogic := 'U';
    SIGNAL D24_ipd             : std_ulogic := 'U';
    SIGNAL D25_ipd             : std_ulogic := 'U';
    SIGNAL D26_ipd             : std_ulogic := 'U';
    SIGNAL D27_ipd             : std_ulogic := 'U';
    SIGNAL D28_ipd             : std_ulogic := 'U';
    SIGNAL D29_ipd             : std_ulogic := 'U';
    SIGNAL D30_ipd             : std_ulogic := 'U';
    SIGNAL D31_ipd             : std_ulogic := 'U';
    SIGNAL D32_ipd             : std_ulogic := 'U';
    SIGNAL D33_ipd             : std_ulogic := 'U';
    SIGNAL D34_ipd             : std_ulogic := 'U';
    SIGNAL D35_ipd             : std_ulogic := 'U';
    SIGNAL RNeg_ipd            : std_ulogic := 'U';
    SIGNAL WNeg_ipd            : std_ulogic := 'U';
    SIGNAL BW0Neg_ipd          : std_ulogic := 'U';
    SIGNAL BW1Neg_ipd          : std_ulogic := 'U';
    SIGNAL BW2Neg_ipd          : std_ulogic := 'U';
    SIGNAL BW3Neg_ipd          : std_ulogic := 'U';
    SIGNAL K_ipd               : std_ulogic := 'U';
    SIGNAL KNeg_ipd            : std_ulogic := 'U';
    SIGNAL C_ipd               : std_ulogic := 'U';
    SIGNAL CNeg_ipd            : std_ulogic := 'U';
    SIGNAL TMS_ipd             : std_ulogic := 'U';
    SIGNAL TDI_ipd             : std_ulogic := 'U';
    SIGNAL TCK_ipd             : std_ulogic := 'U';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (DLLNeg_ipd, DLLNeg, tipd_DLLNeg);
        w_2 : VitalWireDelay (ZQ_ipd, ZQ, tipd_ZQ);
        w_3 : VitalWireDelay (A0_ipd, A0, tipd_A0);
        w_4 : VitalWireDelay (A1_ipd, A1, tipd_A1);
        w_5 : VitalWireDelay (A2_ipd, A2, tipd_A2);
        w_6 : VitalWireDelay (A3_ipd, A3, tipd_A3);
        w_7 : VitalWireDelay (A4_ipd, A4, tipd_A4);
        w_8 : VitalWireDelay (A5_ipd, A5, tipd_A5);
        w_9 : VitalWireDelay (A6_ipd, A6, tipd_A6);
        w_10 : VitalWireDelay (A7_ipd, A7, tipd_A7);
        w_11 : VitalWireDelay (A8_ipd, A8, tipd_A8);
        w_12 : VitalWireDelay (A9_ipd, A9, tipd_A9);
        w_13 : VitalWireDelay (A10_ipd, A10, tipd_A10);
        w_14 : VitalWireDelay (A11_ipd, A11, tipd_A11);
        w_15 : VitalWireDelay (A12_ipd, A12, tipd_A12);
        w_16 : VitalWireDelay (A13_ipd, A13, tipd_A13);
        w_17 : VitalWireDelay (A14_ipd, A14, tipd_A14);
        w_18 : VitalWireDelay (A15_ipd, A15, tipd_A15);
        w_19 : VitalWireDelay (A16_ipd, A16, tipd_A16);
        w_20 : VitalWireDelay (A17_ipd, A17, tipd_A17);
        w_21 : VitalWireDelay (A18_ipd, A18, tipd_A18);
        w_25 : VitalWireDelay (D0_ipd, D0, tipd_D0);
        w_26 : VitalWireDelay (D1_ipd, D1, tipd_D1);
        w_27 : VitalWireDelay (D2_ipd, D2, tipd_D2);
        w_28 : VitalWireDelay (D3_ipd, D3, tipd_D3);
        w_29 : VitalWireDelay (D4_ipd, D4, tipd_D4);
        w_30 : VitalWireDelay (D5_ipd, D5, tipd_D5);
        w_31 : VitalWireDelay (D6_ipd, D6, tipd_D6);
        w_32 : VitalWireDelay (D7_ipd, D7, tipd_D7);
        w_33 : VitalWireDelay (D8_ipd, D8, tipd_D8);
        w_34 : VitalWireDelay (D9_ipd, D9, tipd_D9);
        w_35 : VitalWireDelay (D10_ipd, D10, tipd_D10);
        w_36 : VitalWireDelay (D11_ipd, D11, tipd_D11);
        w_37 : VitalWireDelay (D12_ipd, D12, tipd_D12);
        w_38 : VitalWireDelay (D13_ipd, D13, tipd_D13);
        w_39 : VitalWireDelay (D14_ipd, D14, tipd_D14);
        w_40 : VitalWireDelay (D15_ipd, D15, tipd_D15);
        w_41 : VitalWireDelay (D16_ipd, D16, tipd_D16);
        w_42 : VitalWireDelay (D17_ipd, D17, tipd_D17);
        w_43 : VitalWireDelay (D18_ipd, D18, tipd_D18);
        w_44 : VitalWireDelay (D19_ipd, D19, tipd_D19);
        w_45 : VitalWireDelay (D20_ipd, D20, tipd_D20);
        w_46 : VitalWireDelay (D21_ipd, D21, tipd_D21);
        w_47 : VitalWireDelay (D22_ipd, D22, tipd_D22);
        w_48 : VitalWireDelay (D23_ipd, D23, tipd_D23);
        w_49 : VitalWireDelay (D24_ipd, D24, tipd_D24);
        w_50 : VitalWireDelay (D25_ipd, D25, tipd_D25);
        w_51 : VitalWireDelay (D26_ipd, D26, tipd_D26);
        w_52 : VitalWireDelay (D27_ipd, D27, tipd_D27);
        w_53 : VitalWireDelay (D28_ipd, D28, tipd_D28);
        w_54 : VitalWireDelay (D29_ipd, D29, tipd_D29);
        w_55 : VitalWireDelay (D30_ipd, D30, tipd_D30);
        w_56 : VitalWireDelay (D31_ipd, D31, tipd_D31);
        w_57 : VitalWireDelay (D32_ipd, D32, tipd_D32);
        w_58 : VitalWireDelay (D33_ipd, D33, tipd_D33);
        w_59 : VitalWireDelay (D34_ipd, D34, tipd_D34);
        w_60 : VitalWireDelay (D35_ipd, D35, tipd_D35);
        w_61 : VitalWireDelay (RNeg_ipd, RNeg, tipd_RNeg);
        w_62 : VitalWireDelay (WNeg_ipd, WNeg, tipd_WNeg);
        w_63 : VitalWireDelay (BW0Neg_ipd, BW0Neg, tipd_BW0Neg);
        w_64 : VitalWireDelay (BW1Neg_ipd, BW1Neg, tipd_BW1Neg);
        w_65 : VitalWireDelay (BW2Neg_ipd, BW2Neg, tipd_BW2Neg);
        w_66 : VitalWireDelay (BW3Neg_ipd, BW3Neg, tipd_BW3Neg);
        w_67 : VitalWireDelay (K_ipd, K, tipd_K);
        w_68 : VitalWireDelay (KNeg_ipd, KNeg, tipd_KNeg);
        w_69 : VitalWireDelay (C_ipd, C, tipd_C);
        w_70 : VitalWireDelay (CNeg_ipd, CNeg, tipd_CNeg);
        w_71 : VitalWireDelay (TMS_ipd, TMS, tipd_TMS);
        w_72 : VitalWireDelay (TDI_ipd, TDI, tipd_TDI);
        w_73 : VitalWireDelay (TCK_ipd, TCK, tipd_TCK);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Main Behavior Block
    ----------------------------------------------------------------------------
    Behavior: BLOCK
        PORT (
            DLLNegIn        : IN    std_logic  := 'U';
            BW0NIn          : IN    std_ulogic := 'U';
            BW1NIn          : IN    std_ulogic := 'U';
            BW2NIn          : IN    std_ulogic := 'U';
            BW3NIn          : IN    std_ulogic := 'U';
            Dat0In          : IN    std_logic_vector(HiDbit downto 0);
            Dat1In          : IN    std_logic_vector(HiDbit downto 0);
            Dat2In          : IN    std_logic_vector(HiDbit downto 0);
            Dat3In          : IN    std_logic_vector(HiDbit downto 0);
            DataOut         : OUT   std_logic_vector(35 downto 0)
                                                     := (others => 'Z');
            CIn             : IN    std_ulogic := 'U';
            CNegIn          : IN    std_ulogic := 'U';
            KIn             : IN    std_ulogic := 'U';
            KNegIn          : IN    std_ulogic := 'U';
            AddressIn       : IN    std_logic_vector(HiAbit downto 0);
            RInt            : IN    std_ulogic := 'U';
            WInt            : IN    std_ulogic := 'U';
            CQOut           : OUT   std_ulogic := 'U';
            CQNegOut        : OUT   std_ulogic := 'U'
        );
        PORT MAP (
            Dat0In(0) => D0_ipd,
            Dat0In(1) => D1_ipd,
            Dat0In(2) => D2_ipd,
            Dat0In(3) => D3_ipd,
            Dat0In(4) => D4_ipd,
            Dat0In(5) => D5_ipd,
            Dat0In(6) => D6_ipd,
            Dat0In(7) => D7_ipd,
            Dat0In(8) => D8_ipd,
            Dat1In(0) => D9_ipd,
            Dat1In(1) => D10_ipd,
            Dat1In(2) => D11_ipd,
            Dat1In(3) => D12_ipd,
            Dat1In(4) => D13_ipd,
            Dat1In(5) => D14_ipd,
            Dat1In(6) => D15_ipd,
            Dat1In(7) => D16_ipd,
            Dat1In(8) => D17_ipd,
            Dat2In(0) => D18_ipd,
            Dat2In(1) => D19_ipd,
            Dat2In(2) => D20_ipd,
            Dat2In(3) => D21_ipd,
            Dat2In(4) => D22_ipd,
            Dat2In(5) => D23_ipd,
            Dat2In(6) => D24_ipd,
            Dat2In(7) => D25_ipd,
            Dat2In(8) => D26_ipd,
            Dat3In(0) => D27_ipd,
            Dat3In(1) => D28_ipd,
            Dat3In(2) => D29_ipd,
            Dat3In(3) => D30_ipd,
            Dat3In(4) => D31_ipd,
            Dat3In(5) => D32_ipd,
            Dat3In(6) => D33_ipd,
            Dat3In(7) => D34_ipd,
            Dat3In(8) => D35_ipd,
            DataOut(0) =>  Q0,
            DataOut(1) =>  Q1,
            DataOut(2) =>  Q2,
            DataOut(3) =>  Q3,
            DataOut(4) =>  Q4,
            DataOut(5) =>  Q5,
            DataOut(6) =>  Q6,
            DataOut(7) =>  Q7,
            DataOut(8) =>  Q8,
            DataOut(9) =>  Q9,
            DataOut(10) =>  Q10,
            DataOut(11) =>  Q11,
            DataOut(12) =>  Q12,
            DataOut(13) =>  Q13,
            DataOut(14) =>  Q14,
            DataOut(15) =>  Q15,
            DataOut(16) =>  Q16,
            DataOut(17) =>  Q17,
            DataOut(18) =>  Q18,
            DataOut(19) =>  Q19,
            DataOut(20) =>  Q20,
            DataOut(21) =>  Q21,
            DataOut(22) =>  Q22,
            DataOut(23) =>  Q23,
            DataOut(24) =>  Q24,
            DataOut(25) =>  Q25,
            DataOut(26) =>  Q26,
            DataOut(27) =>  Q27,
            DataOut(28) =>  Q28,
            DataOut(29) =>  Q29,
            DataOut(30) =>  Q30,
            DataOut(31) =>  Q31,
            DataOut(32) =>  Q32,
            DataOut(33) =>  Q33,
            DataOut(34) =>  Q34,
            DataOut(35) =>  Q35,
            AddressIn(0) => A0_ipd,
            AddressIn(1) => A1_ipd,
            AddressIn(2) => A2_ipd,
            AddressIn(3) => A3_ipd,
            AddressIn(4) => A4_ipd,
            AddressIn(5) => A5_ipd,
            AddressIn(6) => A6_ipd,
            AddressIn(7) => A7_ipd,
            AddressIn(8) => A8_ipd,
            AddressIn(9) => A9_ipd,
            AddressIn(10) => A10_ipd,
            AddressIn(11) => A11_ipd,
            AddressIn(12) => A12_ipd,
            AddressIn(13) => A13_ipd,
            AddressIn(14) => A14_ipd,
            AddressIn(15) => A15_ipd,
            AddressIn(16) => A16_ipd,
            AddressIn(17) => A17_ipd,
            AddressIn(18) => A18_ipd,
            BW0NIn => BW0Neg_ipd,
            BW1NIn => BW1Neg_ipd,
            BW2NIn => BW2Neg_ipd,
            BW3NIn => BW3Neg_ipd,
            CIn => C_ipd,
            CNegIn => CNeg_ipd,
            KIn => K_ipd,
            KNegIn => KNeg_ipd,
            RInt => RNeg_ipd,
            WInt => WNeg_ipd,
            CQOut => CQ,
            CQNegOut => CQNeg,
            DLLNegIn => DLLNeg_ipd
        );

        SIGNAL Q_zd     : std_logic_vector(35 DOWNTO 0);
        SIGNAL KTRIG    : std_ulogic;
        SIGNAL CTRIG    : std_ulogic;
        SIGNAL KCTRIG   : std_ulogic;
        SIGNAL KCTRIGN  : std_ulogic;
        SIGNAL CPERIOD  : time := 4 ns;       -- C period
        SIGNAL KPERIOD  : time := 4 ns;
        SIGNAL CInt     : std_ulogic := '0';
        SIGNAL CNegInt  : std_ulogic := '0';