idt703399.vhd

vhdl cod for ram.For sp3e

        w_71 : VitalWireDelay (IOR5_ipd, IOR5, tipd_IOR5);
        w_72 : VitalWireDelay (IOR4_ipd, IOR4, tipd_IOR4);
        w_73 : VitalWireDelay (IOR3_ipd, IOR3, tipd_IOR3);
        w_74 : VitalWireDelay (IOR2_ipd, IOR2, tipd_IOR2);
        w_75 : VitalWireDelay (IOR1_ipd, IOR1, tipd_IOR1);
        w_76 : VitalWireDelay (IOR0_ipd, IOR0, tipd_IOR0);
        w_77 : VitalWireDelay (IOL17_ipd, IOL17, tipd_IOL17);
        w_78 : VitalWireDelay (IOL16_ipd, IOL16, tipd_IOL16);
        w_79 : VitalWireDelay (IOL15_ipd, IOL15, tipd_IOL15);
        w_80 : VitalWireDelay (IOL14_ipd, IOL14, tipd_IOL14);
        w_82 : VitalWireDelay (IOL13_ipd, IOL13, tipd_IOL13);
        w_83 : VitalWireDelay (IOL12_ipd, IOL12, tipd_IOL12);
        w_84 : VitalWireDelay (IOL11_ipd, IOL11, tipd_IOL11);
        w_85 : VitalWireDelay (IOL10_ipd, IOL10, tipd_IOL10);
        w_86 : VitalWireDelay (IOL9_ipd, IOL9, tipd_IOL9);
        w_87 : VitalWireDelay (IOL8_ipd, IOL8, tipd_IOL8);
        w_88 : VitalWireDelay (IOL7_ipd, IOL7, tipd_IOL7);
        w_89 : VitalWireDelay (IOL6_ipd, IOL6, tipd_IOL6);
        w_90 : VitalWireDelay (IOL5_ipd, IOL5, tipd_IOL5);
        w_91 : VitalWireDelay (IOL4_ipd, IOL4, tipd_IOL4);
        w_92 : VitalWireDelay (IOL3_ipd, IOL3, tipd_IOL3);
        w_93 : VitalWireDelay (IOL2_ipd, IOL2, tipd_IOL2);
        w_94 : VitalWireDelay (IOL1_ipd, IOL1, tipd_IOL1);
        w_95 : VitalWireDelay (IOL0_ipd, IOL0, tipd_IOL0);
        w_96 : VitalWireDelay (TDI_ipd, TDI, tipd_TDI);
        w_97 : VitalWireDelay (TCK_ipd, TCK, tipd_TCK);
        w_98 : VitalWireDelay (TMS_ipd, TMS, tipd_TMS);
        w_99 : VitalWireDelay (TRSTNeg_ipd, TRSTNeg, tipd_TRSTNeg);
        w_100 : VitalWireDelay (OPTR_ipd, OPTR, tipd_OPTR);
        w_101 : VitalWireDelay (OPTL_ipd, OPTL, tipd_OPTL);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Main Behavior Block
    ----------------------------------------------------------------------------
    Behavior: BLOCK

        PORT (
            ALIn         : IN    std_logic_vector(HiAbit downto 0);
            ARIn         : IN    std_logic_vector(HiAbit downto 0);
            IOL1In       : IN    std_logic_vector(HiDbit downto 0);
            IOR1In       : IN    std_logic_vector(HiDbit downto 0);
            IOL0In       : IN    std_logic_vector(HiDbit downto 0);
            IOR0In       : IN    std_logic_vector(HiDbit downto 0);
            IOL1Out      : OUT   std_logic_vector(HiDbit downto 0);
            IOR1Out      : OUT   std_logic_vector(HiDbit downto 0);
            IOL0Out      : OUT   std_logic_vector(HiDbit downto 0);
            IOR0Out      : OUT   std_logic_vector(HiDbit downto 0);
            OPTRIn       : IN    std_ulogic := 'U';
            OPTLIn       : IN    std_ulogic := 'U';
            RWLIn        : IN    std_ulogic := 'U';
            RWRIn        : IN    std_ulogic := 'U';
            OELNegIn     : IN    std_ulogic := 'U';
            OERNegIn     : IN    std_ulogic := 'U';
            BE1LNegIn    : IN    std_ulogic := 'U';
            BE0LNegIn    : IN    std_ulogic := 'U';
            BE1RNegIn    : IN    std_ulogic := 'U';
            BE0RNegIn    : IN    std_ulogic := 'U';
            CE0LNegIn    : IN    std_ulogic := 'U';
            CE0RNegIn    : IN    std_ulogic := 'U';
            CE1LIn       : IN    std_ulogic := 'U';
            CE1RIn       : IN    std_ulogic := 'U';
            CLKLIn       : IN    std_ulogic := 'U';
            CLKRIn       : IN    std_ulogic := 'U';
            REPEATLNegIn : IN    std_ulogic := 'U';
            REPEATRNegIn : IN    std_ulogic := 'U';
            CNTENRNegIn  : IN    std_ulogic := 'U';
            CNTENLNegIn  : IN    std_ulogic := 'U';
            ADSRNegIn    : IN    std_ulogic := 'U';
            ADSLNegIn    : IN    std_ulogic := 'U';
            PIPERIn      : IN    std_ulogic := '1';
            PIPELIn      : IN    std_ulogic := '1';
            TDIIn        : IN    std_ulogic := '1';
            TCKIn        : IN    std_ulogic := '1';
            TMSIn        : IN    std_ulogic := '1';
            TRSTNegIn    : IN    std_ulogic := '1'
        );
        PORT MAP (
            ALIn(0) =>  AL0_ipd,
            ALIn(1) =>  AL1_ipd,
            ALIn(2) =>  AL2_ipd,
            ALIn(3) =>  AL3_ipd,
            ALIn(4) =>  AL4_ipd,
            ALIn(5) =>  AL5_ipd,
            ALIn(6) =>  AL6_ipd,
            ALIn(7) =>  AL7_ipd,
            ALIn(8) =>  AL8_ipd,
            ALIn(9) =>  AL9_ipd,
            ALIn(10) =>  AL10_ipd,
            ALIn(11) =>  AL11_ipd,
            ALIn(12) =>  AL12_ipd,
            ALIn(13) =>  AL13_ipd,
            ALIn(14) =>  AL14_ipd,
            ALIn(15) =>  AL15_ipd,
            ALIn(16) =>  AL16_ipd,
            ARIn(0) =>  AR0_ipd,
            ARIn(1) =>  AR1_ipd,
            ARIn(2) =>  AR2_ipd,
            ARIn(3) =>  AR3_ipd,
            ARIn(4) =>  AR4_ipd,
            ARIn(5) =>  AR5_ipd,
            ARIn(6) =>  AR6_ipd,
            ARIn(7) =>  AR7_ipd,
            ARIn(8) =>  AR8_ipd,
            ARIn(9) =>  AR9_ipd,
            ARIn(10) =>  AR10_ipd,
            ARIn(11) =>  AR11_ipd,
            ARIn(12) =>  AR12_ipd,
            ARIn(13) =>  AR13_ipd,
            ARIn(14) =>  AR14_ipd,
            ARIn(15) =>  AR15_ipd,
            ARIn(16) =>  AR16_ipd,
            IOL0In(0) => IOL0_ipd,
            IOL0In(1) => IOL1_ipd,
            IOL0In(2) => IOL2_ipd,
            IOL0In(3) => IOL3_ipd,
            IOL0In(4) => IOL4_ipd,
            IOL0In(5) => IOL5_ipd,
            IOL0In(6) => IOL6_ipd,
            IOL0In(7) => IOL7_ipd,
            IOL0In(8) => IOL8_ipd,
            IOL1In(0) => IOL9_ipd,
            IOL1In(1) => IOL10_ipd,
            IOL1In(2) => IOL11_ipd,
            IOL1In(3) => IOL12_ipd,
            IOL1In(4) => IOL13_ipd,
            IOL1In(5) => IOL14_ipd,
            IOL1In(6) => IOL15_ipd,
            IOL1In(7) => IOL16_ipd,
            IOL1In(8) => IOL17_ipd,
            IOR0In(0) => IOR0_ipd,
            IOR0In(1) => IOR1_ipd,
            IOR0In(2) => IOR2_ipd,
            IOR0In(3) => IOR3_ipd,
            IOR0In(4) => IOR4_ipd,
            IOR0In(5) => IOR5_ipd,
            IOR0In(6) => IOR6_ipd,
            IOR0In(7) => IOR7_ipd,
            IOR0In(8) => IOR8_ipd,
            IOR1In(0) => IOR9_ipd,
            IOR1In(1) => IOR10_ipd,
            IOR1In(2) => IOR11_ipd,
            IOR1In(3) => IOR12_ipd,
            IOR1In(4) => IOR13_ipd,
            IOR1In(5) => IOR14_ipd,
            IOR1In(6) => IOR15_ipd,
            IOR1In(7) => IOR16_ipd,
            IOR1In(8) => IOR17_ipd,
            IOL0Out(0) => IOL0,
            IOL0Out(1) => IOL1,
            IOL0Out(2) => IOL2,
            IOL0Out(3) => IOL3,
            IOL0Out(4) => IOL4,
            IOL0Out(5) => IOL5,
            IOL0Out(6) => IOL6,
            IOL0Out(7) => IOL7,
            IOL0Out(8) => IOL8,
            IOL1Out(0) => IOL9,
            IOL1Out(1) => IOL10,
            IOL1Out(2) => IOL11,
            IOL1Out(3) => IOL12,
            IOL1Out(4) => IOL13,
            IOL1Out(5) => IOL14,
            IOL1Out(6) => IOL15,
            IOL1Out(7) => IOL16,
            IOL1Out(8) => IOL17,
            IOR0Out(0) => IOR0,
            IOR0Out(1) => IOR1,
            IOR0Out(2) => IOR2,
            IOR0Out(3) => IOR3,
            IOR0Out(4) => IOR4,
            IOR0Out(5) => IOR5,
            IOR0Out(6) => IOR6,
            IOR0Out(7) => IOR7,
            IOR0Out(8) => IOR8,
            IOR1Out(0) => IOR9,
            IOR1Out(1) => IOR10,
            IOR1Out(2) => IOR11,
            IOR1Out(3) => IOR12,
            IOR1Out(4) => IOR13,
            IOR1Out(5) => IOR14,
            IOR1Out(6) => IOR15,
            IOR1Out(7) => IOR16,
            IOR1Out(8) => IOR17,
            OPTRIn    => OPTR_ipd,
            OPTLIn    => OPTL_ipd,
            RWLIn     => RWL_ipd,
            RWRIn     => RWR_ipd,
            OELNegIn  => OELNeg_ipd,
            OERNegIn  => OERNeg_ipd,
            BE1RNegIn  => BE1RNeg_ipd,
            BE0RNegIn  => BE0RNeg_ipd,
            BE1LNegIn  => BE1LNeg_ipd,
            BE0LNegIn  => BE0LNeg_ipd,
            CE0LNegIn  => CE0LNeg_ipd,
            CE0RNegIn  => CE0RNeg_ipd,
            CE1LIn  => CE1L_ipd,
            CE1RIn  => CE1R_ipd,
            CLKLIn  => CLKL_ipd,
            CLKRIn  => CLKR_ipd,
            REPEATLNegIn  => REPEATLNeg_ipd,
            REPEATRNegIn  => REPEATRNeg_ipd,
            CNTENRNegIn  => CNTENRNeg_ipd,
            CNTENLNegIn  => CNTENLNeg_ipd,
            ADSRNegIn  => ADSRNeg_ipd,
            ADSLNegIn  => ADSLNeg_ipd,
            PIPELIn   => to_UX01(PIPEL_ipd),
            PIPERIn   => to_UX01(PIPER_ipd),
            TDIIn   => to_UX01(TDI_ipd),
            TCKIn   => to_UX01(TCK_ipd),
            TMSIn   => to_UX01(TMS_ipd),
            TRSTNegIn   => to_UX01(TRSTNeg_ipd)
        );

        SIGNAL IOL1_zd      : std_logic_vector(HiDbit DOWNTO 0);
        SIGNAL IOL0_zd      : std_logic_vector(HiDbit DOWNTO 0);
        SIGNAL IOR1_zd      : std_logic_vector(HiDbit DOWNTO 0);
        SIGNAL IOR0_zd      : std_logic_vector(HiDbit DOWNTO 0);
        SIGNAL BSR_READ     : boolean := false;
        SIGNAL Tri_Outs     : boolean := false;
        SIGNAL EXTST        : boolean := false;
        SIGNAL bsr          : std_logic_vector(bsr_size - 1 downto 0) :=
                                  (OTHERS => '0');

    BEGIN

        ------------------------------------------------------------------------
        -- Behavior Process
        ------------------------------------------------------------------------
        Memory : PROCESS (OELNegIn, OERNegIn, RWLIn, RWRIn, CE0LNegIn,
                          CE0RNegIn, ALIn, ARIn, IOL0In, IOR0In, CE1LIn, CE1RIn,
                          CLKLIn, CLKRIn, REPEATLNegIn, REPEATRNegIn,
                          CNTENRNegIn, CNTENLNegIn, ADSRNegIn, ADSLNegIn,
                          PIPERIn, PIPELIn, IOL1In, IOR1In, BE1RNegIn,
                          BE1LNegIn, BE0RNegIn, BE0LNegIn, BSR_READ, Tri_Outs)

            -- Timing Check Variables
            VARIABLE Tviol_ALIn_CLKLIn         : X01 := '0';
            VARIABLE TD_ALIn_CLKLIn            : VitalTimingDataType;

            VARIABLE Tviol_ARIn_CLKRIn         : X01 := '0';
            VARIABLE TD_ARIn_CLKRIn            : VitalTimingDataType;

            VARIABLE Tviol_CE0LNegIn_CLKLIn    :  X01 := '0';
            VARIABLE TD_CE0LNegIn_CLKLIn       : VitalTimingDataType;

            VARIABLE Tviol_CE0RNegIn_CLKRIn    :  X01 := '0';
            VARIABLE TD_CE0RNegIn_CLKRIn       : VitalTimingDataType;

            VARIABLE Tviol_CE1LIn_CLKLIn       :  X01 := '0';
            VARIABLE TD_CE1LIn_CLKLIn          : VitalTimingDataType;

            VARIABLE Tviol_CE1RIn_CLKRIn       :  X01 := '0';
            VARIABLE TD_CE1RIn_CLKRIn          : VitalTimingDataType;

            VARIABLE Tviol_RWLIn_CLKLIn        : X01 := '0';
            VARIABLE TD_RWLIn_CLKLIn           : VitalTimingDataType;

            VARIABLE Tviol_RWRIn_CLKRIn        : X01 := '0';