idt703319prf.vhd

vhdl cod for ram.For sp3e

        AR2             : IN    std_ulogic := 'U';
        AR3             : IN    std_ulogic := 'U';
        AR4             : IN    std_ulogic := 'U';
        AR5             : IN    std_ulogic := 'U';
        AR6             : IN    std_ulogic := 'U';
        AR7             : IN    std_ulogic := 'U';
        AR8             : IN    std_ulogic := 'U';
        AR9             : IN    std_ulogic := 'U';
        AR10            : IN    std_ulogic := 'U';
        AR11            : IN    std_ulogic := 'U';
        AR12            : IN    std_ulogic := 'U';
        AR13            : IN    std_ulogic := 'U';
        AR14            : IN    std_ulogic := 'U';
        AR15            : IN    std_ulogic := 'U';
        AR16            : IN    std_ulogic := 'U';
        AR17            : IN    std_ulogic := 'U';
        AL0             : IN    std_ulogic := 'U';
        AL1             : IN    std_ulogic := 'U';
        AL2             : IN    std_ulogic := 'U';
        AL3             : IN    std_ulogic := 'U';
        AL4             : IN    std_ulogic := 'U';
        AL5             : IN    std_ulogic := 'U';
        AL6             : IN    std_ulogic := 'U';
        AL7             : IN    std_ulogic := 'U';
        AL8             : IN    std_ulogic := 'U';
        AL9             : IN    std_ulogic := 'U';
        AL10            : IN    std_ulogic := 'U';
        AL11            : IN    std_ulogic := 'U';
        AL12            : IN    std_ulogic := 'U';
        AL13            : IN    std_ulogic := 'U';
        AL14            : IN    std_ulogic := 'U';
        AL15            : IN    std_ulogic := 'U';
        AL16            : IN    std_ulogic := 'U';
        AL17            : IN    std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of idt703319prf : ENTITY IS TRUE;
END idt703319prf;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of idt703319prf IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT partID         : STRING := "IDT703319prf";
    CONSTANT MaxData        : NATURAL := 511;
    CONSTANT TotalLOC       : NATURAL := 262143;
    CONSTANT HiAbit         : NATURAL := 17;
    CONSTANT HiDbit         : NATURAL := 8;
    CONSTANT DataWidth      : NATURAL := 9;

    SIGNAL OPTR_ipd            : std_ulogic := 'U';
    SIGNAL OPTL_ipd            : std_ulogic := 'U';
    SIGNAL RWR_ipd             : std_ulogic := 'U';
    SIGNAL RWL_ipd             : std_ulogic := 'U';
    SIGNAL CE1R_ipd            : std_ulogic := 'U';
    SIGNAL CE1L_ipd            : std_ulogic := 'U';
    SIGNAL CLKR_ipd            : std_ulogic := 'U';
    SIGNAL CLKL_ipd            : std_ulogic := 'U';
    SIGNAL CNTENRNeg_ipd       : std_ulogic := 'U';
    SIGNAL CNTENLNeg_ipd       : std_ulogic := 'U';
    SIGNAL REPEATRNeg_ipd      : std_ulogic := 'U';
    SIGNAL REPEATLNeg_ipd      : std_ulogic := 'U';
    SIGNAL ADSRNeg_ipd         : std_ulogic := 'U';
    SIGNAL ADSLNeg_ipd         : std_ulogic := 'U';
    SIGNAL CE0RNeg_ipd         : std_ulogic := 'U';
    SIGNAL CE0LNeg_ipd         : std_ulogic := 'U';
    SIGNAL OERNeg_ipd          : std_ulogic := 'U';
    SIGNAL OELNeg_ipd          : std_ulogic := 'U';
    SIGNAL BE1RNeg_ipd         : std_ulogic := 'U';
    SIGNAL BE0RNeg_ipd         : std_ulogic := 'U';
    SIGNAL BE1LNeg_ipd         : std_ulogic := 'U';
    SIGNAL BE0LNeg_ipd         : std_ulogic := 'U';
    SIGNAL IOR17_ipd           : std_ulogic := 'U';
    SIGNAL IOR16_ipd           : std_ulogic := 'U';
    SIGNAL IOR15_ipd           : std_ulogic := 'U';
    SIGNAL IOR14_ipd           : std_ulogic := 'U';
    SIGNAL IOR13_ipd           : std_ulogic := 'U';
    SIGNAL IOR12_ipd           : std_ulogic := 'U';
    SIGNAL IOR11_ipd           : std_ulogic := 'U';
    SIGNAL IOR10_ipd           : std_ulogic := 'U';
    SIGNAL IOR9_ipd            : std_ulogic := 'U';
    SIGNAL IOR8_ipd            : std_ulogic := 'U';
    SIGNAL IOR7_ipd            : std_ulogic := 'U';
    SIGNAL IOR6_ipd            : std_ulogic := 'U';
    SIGNAL IOR5_ipd            : std_ulogic := 'U';
    SIGNAL IOR4_ipd            : std_ulogic := 'U';
    SIGNAL IOR3_ipd            : std_ulogic := 'U';
    SIGNAL IOR2_ipd            : std_ulogic := 'U';
    SIGNAL IOR1_ipd            : std_ulogic := 'U';
    SIGNAL IOR0_ipd            : std_ulogic := 'U';
    SIGNAL IOL17_ipd           : std_ulogic := 'U';
    SIGNAL IOL16_ipd           : std_ulogic := 'U';
    SIGNAL IOL15_ipd           : std_ulogic := 'U';
    SIGNAL IOL14_ipd           : std_ulogic := 'U';
    SIGNAL IOL13_ipd           : std_ulogic := 'U';
    SIGNAL IOL12_ipd           : std_ulogic := 'U';
    SIGNAL IOL11_ipd           : std_ulogic := 'U';
    SIGNAL IOL10_ipd           : std_ulogic := 'U';
    SIGNAL IOL9_ipd            : std_ulogic := 'U';
    SIGNAL IOL8_ipd            : std_ulogic := 'U';
    SIGNAL IOL7_ipd            : std_ulogic := 'U';
    SIGNAL IOL6_ipd            : std_ulogic := 'U';
    SIGNAL IOL5_ipd            : std_ulogic := 'U';
    SIGNAL IOL4_ipd            : std_ulogic := 'U';
    SIGNAL IOL3_ipd            : std_ulogic := 'U';
    SIGNAL IOL2_ipd            : std_ulogic := 'U';
    SIGNAL IOL1_ipd            : std_ulogic := 'U';
    SIGNAL IOL0_ipd            : std_ulogic := 'U';
    SIGNAL AR0_ipd             : std_ulogic := 'U';
    SIGNAL AR1_ipd             : std_ulogic := 'U';
    SIGNAL AR2_ipd             : std_ulogic := 'U';
    SIGNAL AR3_ipd             : std_ulogic := 'U';
    SIGNAL AR4_ipd             : std_ulogic := 'U';
    SIGNAL AR5_ipd             : std_ulogic := 'U';
    SIGNAL AR6_ipd             : std_ulogic := 'U';
    SIGNAL AR7_ipd             : std_ulogic := 'U';
    SIGNAL AR8_ipd             : std_ulogic := 'U';
    SIGNAL AR9_ipd             : std_ulogic := 'U';
    SIGNAL AR10_ipd            : std_ulogic := 'U';
    SIGNAL AR11_ipd            : std_ulogic := 'U';
    SIGNAL AR12_ipd            : std_ulogic := 'U';
    SIGNAL AR13_ipd            : std_ulogic := 'U';
    SIGNAL AR14_ipd            : std_ulogic := 'U';
    SIGNAL AR15_ipd            : std_ulogic := 'U';
    SIGNAL AR16_ipd            : std_ulogic := 'U';
    SIGNAL AR17_ipd            : std_ulogic := 'U';
    SIGNAL AL0_ipd             : std_ulogic := 'U';
    SIGNAL AL1_ipd             : std_ulogic := 'U';
    SIGNAL AL2_ipd             : std_ulogic := 'U';
    SIGNAL AL3_ipd             : std_ulogic := 'U';
    SIGNAL AL4_ipd             : std_ulogic := 'U';
    SIGNAL AL5_ipd             : std_ulogic := 'U';
    SIGNAL AL6_ipd             : std_ulogic := 'U';
    SIGNAL AL7_ipd             : std_ulogic := 'U';
    SIGNAL AL8_ipd             : std_ulogic := 'U';
    SIGNAL AL9_ipd             : std_ulogic := 'U';
    SIGNAL AL10_ipd            : std_ulogic := 'U';
    SIGNAL AL11_ipd            : std_ulogic := 'U';
    SIGNAL AL12_ipd            : std_ulogic := 'U';
    SIGNAL AL13_ipd            : std_ulogic := 'U';
    SIGNAL AL14_ipd            : std_ulogic := 'U';
    SIGNAL AL15_ipd            : std_ulogic := 'U';
    SIGNAL AL16_ipd            : std_ulogic := 'U';
    SIGNAL AL17_ipd            : std_ulogic := 'U';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (RWR_ipd, RWR, tipd_RWR);
        w_2 : VitalWireDelay (RWL_ipd, RWL, tipd_RWL);
        w_3 : VitalWireDelay (CE1R_ipd, CE1R, tipd_CE1R);
        w_4 : VitalWireDelay (CE1L_ipd, CE1L, tipd_CE1L);
        w_7 : VitalWireDelay (CLKR_ipd, CLKR, tipd_CLKR);
        w_8 : VitalWireDelay (CLKL_ipd, CLKL, tipd_CLKL);
        w_9 : VitalWireDelay (CNTENRNeg_ipd, CNTENRNeg, tipd_CNTENRNeg);
        w_10 : VitalWireDelay (CNTENLNeg_ipd, CNTENLNeg, tipd_CNTENLNeg);
        w_11 : VitalWireDelay (REPEATRNeg_ipd, REPEATRNeg, tipd_REPEATRNeg);
        w_12 : VitalWireDelay (REPEATLNeg_ipd, REPEATLNeg, tipd_REPEATLNeg);
        w_13 : VitalWireDelay (ADSRNeg_ipd, ADSRNeg, tipd_ADSRNeg);
        w_14 : VitalWireDelay (ADSLNeg_ipd, ADSLNeg, tipd_ADSLNeg);
        w_15 : VitalWireDelay (CE0RNeg_ipd, CE0RNeg, tipd_CE0RNeg);
        w_16 : VitalWireDelay (CE0LNeg_ipd, CE0LNeg, tipd_CE0LNeg);
        w_17 : VitalWireDelay (OERNeg_ipd, OERNeg, tipd_OERNeg);
        w_18 : VitalWireDelay (OELNeg_ipd, OELNeg, tipd_OELNeg);
        w_19 : VitalWireDelay (BE1RNeg_ipd, BE1RNeg, tipd_BE1RNeg);
        w_20 : VitalWireDelay (BE0RNeg_ipd, BE0RNeg, tipd_BE0RNeg);
        w_21 : VitalWireDelay (BE1LNeg_ipd, BE1LNeg, tipd_BE1LNeg);
        w_22 : VitalWireDelay (BE0LNeg_ipd, BE0LNeg, tipd_BE0LNeg);
        w_23 : VitalWireDelay (AR0_ipd, AR0, tipd_AR0);
        w_24 : VitalWireDelay (AR1_ipd, AR1, tipd_AR1);
        w_25 : VitalWireDelay (AR2_ipd, AR2, tipd_AR2);
        w_26 : VitalWireDelay (AR3_ipd, AR3, tipd_AR3);
        w_27 : VitalWireDelay (AR4_ipd, AR4, tipd_AR4);
        w_28 : VitalWireDelay (AR5_ipd, AR5, tipd_AR5);
        w_29 : VitalWireDelay (AR6_ipd, AR6, tipd_AR6);
        w_30 : VitalWireDelay (AR7_ipd, AR7, tipd_AR7);
        w_31 : VitalWireDelay (AR8_ipd, AR8, tipd_AR8);
        w_32 : VitalWireDelay (AR9_ipd, AR9, tipd_AR9);
        w_33 : VitalWireDelay (AR10_ipd, AR10, tipd_AR10);
        w_34 : VitalWireDelay (AR11_ipd, AR11, tipd_AR11);
        w_35 : VitalWireDelay (AR12_ipd, AR12, tipd_AR12);
        w_36 : VitalWireDelay (AR13_ipd, AR13, tipd_AR13);
        w_37 : VitalWireDelay (AR14_ipd, AR14, tipd_AR14);
        w_38 : VitalWireDelay (AR15_ipd, AR15, tipd_AR15);
        w_39 : VitalWireDelay (AR16_ipd, AR16, tipd_AR16);
        w_40 : VitalWireDelay (AR17_ipd, AR17, tipd_AR17);
        w_41 : VitalWireDelay (AL0_ipd, AL0, tipd_AL0);
        w_42 : VitalWireDelay (AL1_ipd, AL1, tipd_AL1);
        w_43 : VitalWireDelay (AL2_ipd, AL2, tipd_AL2);
        w_44 : VitalWireDelay (AL3_ipd, AL3, tipd_AL3);
        w_45 : VitalWireDelay (AL4_ipd, AL4, tipd_AL4);
        w_46 : VitalWireDelay (AL5_ipd, AL5, tipd_AL5);
        w_47 : VitalWireDelay (AL6_ipd, AL6, tipd_AL6);
        w_48 : VitalWireDelay (AL7_ipd, AL7, tipd_AL7);
        w_49 : VitalWireDelay (AL8_ipd, AL8, tipd_AL8);
        w_50 : VitalWireDelay (AL9_ipd, AL9, tipd_AL9);
        w_51 : VitalWireDelay (AL10_ipd, AL10, tipd_AL10);
        w_52 : VitalWireDelay (AL11_ipd, AL11, tipd_AL11);
        w_53 : VitalWireDelay (AL12_ipd, AL12, tipd_AL12);
        w_54 : VitalWireDelay (AL13_ipd, AL13, tipd_AL13);
        w_55 : VitalWireDelay (AL14_ipd, AL14, tipd_AL14);
        w_56 : VitalWireDelay (AL15_ipd, AL15, tipd_AL15);
        w_57 : VitalWireDelay (AL16_ipd, AL16, tipd_AL16);
        w_58 : VitalWireDelay (AL17_ipd, AL17, tipd_AL17);
        w_59 : VitalWireDelay (IOR17_ipd, IOR17, tipd_IOR17);
        w_60 : VitalWireDelay (IOR16_ipd, IOR16, tipd_IOR16);
        w_61 : VitalWireDelay (IOR15_ipd, IOR15, tipd_IOR15);
        w_62 : VitalWireDelay (IOR14_ipd, IOR14, tipd_IOR14);
        w_63 : VitalWireDelay (IOR13_ipd, IOR13, tipd_IOR13);
        w_64 : VitalWireDelay (IOR12_ipd, IOR12, tipd_IOR12);
        w_65 : VitalWireDelay (IOR11_ipd, IOR11, tipd_IOR11);
        w_66 : VitalWireDelay (IOR10_ipd, IOR10, tipd_IOR10);
        w_67 : VitalWireDelay (IOR9_ipd, IOR9, tipd_IOR9);
        w_68 : VitalWireDelay (IOR8_ipd, IOR8, tipd_IOR8);
        w_69 : VitalWireDelay (IOR7_ipd, IOR7, tipd_IOR7);
        w_70 : VitalWireDelay (IOR6_ipd, IOR6, tipd_IOR6);
        w_71 : VitalWireDelay (IOR5_ipd, IOR5, tipd_IOR5);
        w_72 : VitalWireDelay (IOR4_ipd, IOR4, tipd_IOR4);
        w_73 : VitalWireDelay (IOR3_ipd, IOR3, tipd_IOR3);
        w_74 : VitalWireDelay (IOR2_ipd, IOR2, tipd_IOR2);
        w_75 : VitalWireDelay (IOR1_ipd, IOR1, tipd_IOR1);
        w_76 : VitalWireDelay (IOR0_ipd, IOR0, tipd_IOR0);
        w_77 : VitalWireDelay (IOL17_ipd, IOL17, tipd_IOL17);
        w_78 : VitalWireDelay (IOL16_ipd, IOL16, tipd_IOL16);
        w_79 : VitalWireDelay (IOL15_ipd, IOL15, tipd_IOL15);
        w_80 : VitalWireDelay (IOL14_ipd, IOL14, tipd_IOL14);
        w_82 : VitalWireDelay (IOL13_ipd, IOL13, tipd_IOL13);
        w_83 : VitalWireDelay (IOL12_ipd, IOL12, tipd_IOL12);
        w_84 : VitalWireDelay (IOL11_ipd, IOL11, tipd_IOL11);
        w_85 : VitalWireDelay (IOL10_ipd, IOL10, tipd_IOL10);
        w_86 : VitalWireDelay (IOL9_ipd, IOL9, tipd_IOL9);
        w_87 : VitalWireDelay (IOL8_ipd, IOL8, tipd_IOL8);
        w_88 : VitalWireDelay (IOL7_ipd, IOL7, tipd_IOL7);
        w_89 : VitalWireDelay (IOL6_ipd, IOL6, tipd_IOL6);
        w_90 : VitalWireDelay (IOL5_ipd, IOL5, tipd_IOL5);
        w_91 : VitalWireDelay (IOL4_ipd, IOL4, tipd_IOL4);
        w_92 : VitalWireDelay (IOL3_ipd, IOL3, tipd_IOL3);
        w_93 : VitalWireDelay (IOL2_ipd, IOL2, tipd_IOL2);
        w_94 : VitalWireDelay (IOL1_ipd, IOL1, tipd_IOL1);
        w_95 : VitalWireDelay (IOL0_ipd, IOL0, tipd_IOL0);
        w_100 : VitalWireDelay (OPTR_ipd, OPTR, tipd_OPTR);
        w_101 : VitalWireDelay (OPTL_ipd, OPTL, tipd_OPTL);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Main Behavior Block
    ----------------------------------------------------------------------------
    Behavior: BLOCK

        PORT (
            ALIn         : IN    std_logic_vector(HiAbit downto 0);
            ARIn         : IN    std_logic_vector(HiAbit downto 0);
            IOL1In       : IN    std_logic_vector(HiDbit downto 0);