idt71016.vhd

vhdl cod for ram.For sp3e

                    TestSignalName  => "BHENeg",
                    RefSignal       => WENegIn,
                    RefSignalName   => "WENeg",
                    SetupHigh       => tsetup_BLENeg_WENeg,
                    SetupLow        => tsetup_BLENeg_WENeg,
                    CheckEnabled    => (CENeg_nwv ='0' and OENeg_nwv ='1'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_BHENeg_WENeg,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_BHENeg_WENeg );

                VitalSetupHoldCheck (
                    TestSignal      => DataHIn,
                    TestSignalName  => "DataH",
                    RefSignal       => CENegIn,
                    RefSignalName   => "CENeg",
                    SetupHigh       => tsetup_D0_CENeg,
                    SetupLow        => tsetup_D0_CENeg,
                    HoldHigh        => thold_D0_CENeg,
                    HoldLow         => thold_D0_CENeg,
                    CheckEnabled    => (WENeg_nwv ='0' and OENeg_nwv ='1' and
                                        BHENeg_nwv = '0'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_D8_CENeg,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_D8_CENeg );

                VitalSetupHoldCheck (
                    TestSignal      => DataLIn,
                    TestSignalName  => "DataL",
                    RefSignal       => CENegIn,
                    RefSignalName   => "CENeg",
                    SetupHigh       => tsetup_D0_CENeg,
                    SetupLow        => tsetup_D0_CENeg,
                    HoldHigh        => thold_D0_CENeg,
                    HoldLow         => thold_D0_CENeg,
                    CheckEnabled    => (WENeg_nwv ='0' and OENeg_nwv ='1' and
                                        BLENeg_nwv = '0'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_D0_CENeg,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_D0_CENeg );

                VitalPeriodPulseCheck (
                    TestSignal      =>  WENegIn,
                    TestSignalName  =>  "WENeg",
                    PulseWidthLow   =>  tpw_WENeg_negedge,
                    PeriodData      =>  PD_WENeg,
                    XOn             =>  XOn,
                    MsgOn           =>  MsgOn,
                    Violation       =>  Pviol_WENeg,
                    HeaderMsg       =>  InstancePath & PartID,
                    CheckEnabled    =>  TRUE );

                Violation := Pviol_WENeg OR Tviol_D0_WENeg OR Tviol_D0_CENeg
                             OR Tviol_D8_WENeg OR Tviol_D8_CENeg OR
                             Tviol_BHENeg_WENeg OR Tviol_BLENeg_WENeg;

                ASSERT Violation = '0'
                    REPORT InstancePath & partID & ": simulation may be" &
                           " inaccurate due to timing violations"
                    SEVERITY SeverityMode;

            END IF; -- Timing Check Section

            --------------------------------------------------------------------
            -- Functional Section
            --------------------------------------------------------------------

            IF (CENeg_nwv = '0') THEN

                Location := To_Nat(AddressIn);

                IF (WENeg_nwv = '1') THEN
                    IF BHENeg_nwv = '0' THEN
                        DataTempH := MemDataH(Location);
                        IF DataTempH >= 0 THEN
                            DataHDrive := To_slv(DataTempH, DataWidth);
                        ELSIF DataTempH = -2 THEN
                            DataHDrive := (OTHERS => 'U');
                        ELSE
                            DataHDrive := (OTHERS => 'X');
                        END IF;
                    ELSE
                        DataHDrive := (OTHERS => 'Z');
                    END IF;
                    IF BLENeg_nwv = '0' THEN
                        DataTempL  := MemDataL(Location);
                        IF DataTempL >= 0 THEN
                            DataLDrive := To_slv(DataTempL, DataWidth);
                        ELSIF DataTempL = -2 THEN
                            DataLDrive := (OTHERS => 'U');
                        ELSE
                            DataLDrive := (OTHERS => 'X');
                        END IF;
                    ELSE
                        DataLDrive := (OTHERS => 'Z');
                    END IF;
                ELSIF (WENeg_nwv = '0') THEN
                    IF Violation = '0' THEN
                        IF BHENeg_nwv = '0' THEN
                            DataTempH := To_Nat(DataHIn);
                        ELSE
                            DataTempH := -1;
                        END IF;
                        IF BLENeg_nwv = '0' THEN
                            DataTempL := To_Nat(DataLIn);
                        ELSE
                            DataTempL := -1;
                        END IF;
                    END IF;
                    MemDataH(Location) := DataTempH;
                    MemDataL(Location) := DataTempL;
                END IF;
            ELSE
                DataHDrive := (OTHERS => 'Z');
                DataLDrive := (OTHERS => 'Z');
            END IF;

            --------------------------------------------------------------------
            -- Output Section
            --------------------------------------------------------------------
            DH_zd <= DataHDrive;
            DL_zd <= DataLDrive;

        END PROCESS;                           

        ------------------------------------------------------------------------
        -- Path Delay Processes generated as a function of data width
        ------------------------------------------------------------------------
        DataOut_Width : FOR i IN HiDbit DOWNTO 0 GENERATE
            DataOut_Delay : PROCESS (DH_zd(i), DL_zd(i), DL_buf(i), DH_buf(i)) 
            VARIABLE DH_GlitchData:VitalGlitchDataArrayType(HiDbit Downto 0);
            VARIABLE DL_GlitchData:VitalGlitchDataArrayType(HiDbit Downto 0);
            VARIABLE DHbuf_GlitchData:VitalGlitchDataArrayType(HiDbit Downto 0);
            VARIABLE DLbuf_GlitchData:VitalGlitchDataArrayType(HiDbit Downto 0);
            BEGIN
                VitalPathDelay01Z (
                    OutSignal       => DH_int(i),
                    OutSignalName   => "DataHaddr",
                    OutTemp         => DH_zd(i),
                    Mode            => OnEvent, 
                    GlitchData      => DH_GlitchData(i),
                    Paths           => (     
                        0 => (InputChangeTime => CENeg_ipd'LAST_EVENT,
                              PathDelay       => tpd_CENeg_D0,
                              PathCondition   => TRUE),   
                        1 => (InputChangeTime => AddressIn'LAST_EVENT,
                              PathDelay => VitalExtendToFillDelay(tpd_A0_D0),
                              PathCondition   => TRUE),
                        2 => (InputChangeTime => BHENeg_ipd'LAST_EVENT,
                              PathDelay       => tpd_BLENeg_D0,
                              PathCondition   => TRUE)   
                    )
                );

                VitalPathDelay01Z (
                    OutSignal       => DL_int(i),
                    OutSignalName   => "DataLaddr",
                    OutTemp         => DL_zd(i),
                    Mode            => OnEvent, 
                    GlitchData      => DL_GlitchData(i),
                    Paths           => (     
                        0 => (InputChangeTime => CENeg_ipd'LAST_EVENT,
                              PathDelay       => tpd_CENeg_D0,
                              PathCondition   => TRUE),   
                        1 => (InputChangeTime => AddressIn'LAST_EVENT,
                              PathDelay => VitalExtendToFillDelay(tpd_A0_D0),
                              PathCondition   => TRUE),
                        2 => (InputChangeTime => BLENeg_ipd'LAST_EVENT,
                              PathDelay       => tpd_BLENeg_D0,
                              PathCondition   => TRUE)   
                    )
                );

                VitalPathDelay01Z (
                    OutSignal       => DataHOut(i),
                    OutSignalName   => "DataH",
                    OutTemp         => DH_buf(i),
                    Mode            => OnEvent, 
                    GlitchData      => DHbuf_GlitchData(i),
                    Paths           => (     
                        0 => (InputChangeTime => OENeg_ipd'LAST_EVENT,
                              PathDelay       => tpd_OENeg_D0,
                              PathCondition   => CENeg_nwv = '0'),
                        1 => (InputChangeTime => DH_int'LAST_EVENT,
                              PathDelay => VitalExtendToFillDelay(0 ns),
                              PathCondition   => OENeg_nwv = '0')
                    )
                );

                VitalPathDelay01Z (
                    OutSignal       => DataLOut(i),
                    OutSignalName   => "DataL",
                    OutTemp         => DL_buf(i),
                    Mode            => OnEvent, 
                    GlitchData      => DLbuf_GlitchData(i),
                    Paths           => (     
                        0 => (InputChangeTime => OENeg_ipd'LAST_EVENT,
                              PathDelay       => tpd_OENeg_D0,
                              PathCondition   => CENeg_nwv = '0'),
                        1 => (InputChangeTime => DL_int'LAST_EVENT,
                              PathDelay => VitalExtendToFillDelay(0 ns),
                              PathCondition   => OENeg_nwv = '0')
                    )
                );

            END PROCESS;                           
        END GENERATE;

    END BLOCK;
END vhdl_behavioral;