idt71016.vhd

vhdl cod for ram.For sp3e

        w_20: VitalWireDelay (D14_ipd, D14, tipd_D14);
        w_21: VitalWireDelay (D15_ipd, D15, tipd_D15);
        w_22: VitalWireDelay (A0_ipd, A0, tipd_A0);
        w_23: VitalWireDelay (A1_ipd, A1, tipd_A1);
        w_24: VitalWireDelay (A2_ipd, A2, tipd_A2);
        w_25: VitalWireDelay (A3_ipd, A3, tipd_A3);
        w_26: VitalWireDelay (A4_ipd, A4, tipd_A4);
        w_27: VitalWireDelay (A5_ipd, A5, tipd_A5);
        w_28: VitalWireDelay (A6_ipd, A6, tipd_A6);
        w_29: VitalWireDelay (A7_ipd, A7, tipd_A7);
        w_30: VitalWireDelay (A8_ipd, A8, tipd_A8);
        w_32: VitalWireDelay (A9_ipd, A9, tipd_A9);
        w_33: VitalWireDelay (A10_ipd, A10, tipd_A10);
        w_34: VitalWireDelay (A11_ipd, A11, tipd_A11);
        w_35: VitalWireDelay (A12_ipd, A12, tipd_A12);
        w_36: VitalWireDelay (A13_ipd, A13, tipd_A13);
        w_37: VitalWireDelay (A14_ipd, A14, tipd_A14);
        w_38: VitalWireDelay (A15_ipd, A15, tipd_A15);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Main Behavior Block
    ----------------------------------------------------------------------------
    Behavior: BLOCK

        PORT (
            AddressIn       : IN    std_logic_vector(HiAbit downto 0);
            DataHIn         : IN    std_logic_vector(HiDbit downto 0);
            DataLIn         : IN    std_logic_vector(HiDbit downto 0);
            DataHOut        : OUT   std_logic_vector(HiDbit downto 0);
            DataLOut        : OUT   std_logic_vector(HiDbit downto 0);
            BHENegIn        : IN    std_ulogic := 'U';
            BLENegIn        : IN    std_ulogic := 'U';
            OENegIn         : IN    std_ulogic := 'U';
            WENegIn         : IN    std_ulogic := 'U';
            CENegIn         : IN    std_ulogic := 'U'
        );
        PORT MAP (
            DataLOut(0) =>  D0,
            DataLOut(1) =>  D1,
            DataLOut(2) =>  D2,
            DataLOut(3) =>  D3,
            DataLOut(4) =>  D4,
            DataLOut(5) =>  D5,
            DataLOut(6) =>  D6,
            DataLOut(7) =>  D7,
            DataHOut(0) =>  D8,
            DataHOut(1) =>  D9,
            DataHOut(2) =>  D10,
            DataHOut(3) =>  D11,
            DataHOut(4) =>  D12,
            DataHOut(5) =>  D13,
            DataHOut(6) =>  D14,
            DataHOut(7) =>  D15,
            DataLIn(0) =>  D0_ipd,
            DataLIn(1) =>  D1_ipd,
            DataLIn(2) =>  D2_ipd,
            DataLIn(3) =>  D3_ipd,
            DataLIn(4) =>  D4_ipd,
            DataLIn(5) =>  D5_ipd,
            DataLIn(6) =>  D6_ipd,
            DataLIn(7) =>  D7_ipd,
            DataHIn(0) =>  D8_ipd,
            DataHIn(1) =>  D9_ipd,
            DataHIn(2) =>  D10_ipd,
            DataHIn(3) =>  D11_ipd,
            DataHIn(4) =>  D12_ipd,
            DataHIn(5) =>  D13_ipd,
            DataHIn(6) =>  D14_ipd,
            DataHIn(7) =>  D15_ipd,
            AddressIn(0) => A0_ipd,
            AddressIn(1) => A1_ipd,
            AddressIn(2) => A2_ipd,
            AddressIn(3) => A3_ipd,
            AddressIn(4) => A4_ipd,
            AddressIn(5) => A5_ipd,
            AddressIn(6) => A6_ipd,
            AddressIn(7) => A7_ipd,
            AddressIn(8) => A8_ipd,
            AddressIn(9) => A9_ipd,
            AddressIn(10) => A10_ipd,
            AddressIn(11) => A11_ipd,
            AddressIn(12) => A12_ipd,
            AddressIn(13) => A13_ipd,
            AddressIn(14) => A14_ipd,
            AddressIn(15) => A15_ipd,
            BHENegIn => BHENeg_ipd,
            BLENegIn => BLENeg_ipd,
            OENegIn => OENeg_ipd,
            WENegIn => WENeg_ipd,
            CENegIn => CENeg_ipd
        );

        SIGNAL DH_zd    : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z');
        SIGNAL DL_zd    : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z');
        SIGNAL DH_int   : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z');
        SIGNAL DL_int   : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z');
        SIGNAL DH_buf   : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z');
        SIGNAL DL_buf   : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z');
        SIGNAL CENeg_nwv : UX01 := 'U';
        SIGNAL OENeg_nwv : UX01 := 'U';

    BEGIN 

        CENeg_nwv   <= To_UX01 (s => CENegIn);
        OENeg_nwv   <= To_UX01 (s => OENegIn);

        ------------------------------------------------------------------------
        -- Tristate Process
        ------------------------------------------------------------------------
        Tristate : PROCESS (OENeg_nwv, DH_int, DL_int)

        BEGIN 
            IF OENeg_nwv = '0' THEN
                DH_buf <= DH_int;
                DL_buf <= DL_int;
            ELSE
                DH_buf <= (OTHERS => 'Z');
                DL_buf <= (OTHERS => 'Z');
            END IF;

        END PROCESS;                           

        ------------------------------------------------------------------------
        -- Behavior Process
        ------------------------------------------------------------------------
        Behavior : PROCESS (OENeg_nwv, WENegIn, CENeg_nwv, AddressIn, DataHIn, 
                            DataLIn, BHENegIn, BLENegIn)
                         
            -- Timing Check Variables
            VARIABLE Tviol_D0_WENeg: X01 := '0';
            VARIABLE TD_D0_WENeg   : VitalTimingDataType;

            VARIABLE Tviol_D8_WENeg: X01 := '0';
            VARIABLE TD_D8_WENeg   : VitalTimingDataType;

            VARIABLE Tviol_BHENeg_WENeg: X01 := '0';
            VARIABLE TD_BHENeg_WENeg   : VitalTimingDataType;

            VARIABLE Tviol_BLENeg_WENeg: X01 := '0';
            VARIABLE TD_BLENeg_WENeg   : VitalTimingDataType;

            VARIABLE Tviol_D8_CENeg: X01 := '0';
            VARIABLE TD_D8_CENeg   : VitalTimingDataType;

            VARIABLE Tviol_D0_CENeg: X01 := '0';
            VARIABLE TD_D0_CENeg   : VitalTimingDataType;

            VARIABLE Pviol_WENeg   : X01 := '0';
            VARIABLE PD_WENeg      : VitalPeriodDataType := VitalPeriodDataInit;

            -- Memory array declaration
            TYPE MemStore IS ARRAY (0 to TotalLOC) OF INTEGER 
                             RANGE  -2 TO MaxData;

            -- Functionality Results Variables
            VARIABLE Violation  : X01 := '0';
            VARIABLE DataHDrive : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'X');
            VARIABLE DataLDrive : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'X');
            VARIABLE DataTempH  : INTEGER RANGE -2 TO MaxData  := -2;
            VARIABLE DataTempL  : INTEGER RANGE -2 TO MaxData  := -2;
            VARIABLE Location   : NATURAL RANGE 0 TO TotalLOC := 0;
            VARIABLE MemDataH   : MemStore;
            VARIABLE MemDataL   : MemStore;

            -- No Weak Values Variables
            VARIABLE BHENeg_nwv  : UX01 := 'X';
            VARIABLE BLENeg_nwv  : UX01 := 'X';
            VARIABLE WENeg_nwv   : UX01 := 'X';

        BEGIN 
            BHENeg_nwv  := To_UX01 (s => BHENegIn);
            BLENeg_nwv  := To_UX01 (s => BLENegIn);
            WENeg_nwv   := To_UX01 (s => WENegIn);

            --------------------------------------------------------------------
            -- Timing Check Section
            --------------------------------------------------------------------
            IF (TimingChecksOn) THEN

                VitalSetupHoldCheck (
                    TestSignal      => DataHIn,
                    TestSignalName  => "DataH",
                    RefSignal       => WENegIn,
                    RefSignalName   => "WENeg",
                    SetupHigh       => tsetup_D0_WENeg,
                    SetupLow        => tsetup_D0_WENeg,
                    HoldHigh        => thold_D0_WENeg,
                    HoldLow         => thold_D0_WENeg,
                    CheckEnabled    => (CENeg_nwv ='0' and OENeg_nwv ='1' and 
                                        BHENeg_nwv = '0'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_D8_WENeg,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_D8_WENeg );

                VitalSetupHoldCheck (
                    TestSignal      => DataLIn,
                    TestSignalName  => "DataL",
                    RefSignal       => WENegIn,
                    RefSignalName   => "WENeg",
                    SetupHigh       => tsetup_D0_WENeg,
                    SetupLow        => tsetup_D0_WENeg,
                    HoldHigh        => thold_D0_WENeg,
                    HoldLow         => thold_D0_WENeg,
                    CheckEnabled    => (CENeg_nwv ='0' and OENeg_nwv ='1' and 
                                        BLENeg_nwv = '0'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_D0_WENeg,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_D0_WENeg );

                VitalSetupHoldCheck (
                    TestSignal      => BHENegIn,