idt71016.vhd

vhdl cod for ram.For sp3e

--------------------------------------------------------------------------------
--  File Name: idt71016.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1999 - 2002 Free Model Foundry; http://www.FreeModelFoundry.com
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0     R. Munden   99 DEC 31   Initial release
--    V2.0     R. Munden   00 JUN 15   Rewrote to correct timing premption by
--                                     OENeg
--    V2.1     R. Munden   02 MAR 07   Corrected timing checks
--    V2.2     R. Munden   02 SEP 03   removed duplicate variable CENeg_nwv
-- 
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:     RAM
--  Technology:  not ECL
--  Part:        IDT71016
-- 
--  Description: 64K X 16 SRAM
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;
                USE FMF.conversions.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY idt71016 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_OENeg          : VitalDelayType01 := VitalZeroDelay01;
        tipd_WENeg          : VitalDelayType01 := VitalZeroDelay01;
        tipd_CENeg          : VitalDelayType01 := VitalZeroDelay01;
        tipd_BHENeg         : VitalDelayType01 := VitalZeroDelay01;
        tipd_BLENeg         : VitalDelayType01 := VitalZeroDelay01;
        tipd_D0             : VitalDelayType01 := VitalZeroDelay01;
        tipd_D1             : VitalDelayType01 := VitalZeroDelay01;
        tipd_D2             : VitalDelayType01 := VitalZeroDelay01;
        tipd_D3             : VitalDelayType01 := VitalZeroDelay01;
        tipd_D4             : VitalDelayType01 := VitalZeroDelay01;
        tipd_D5             : VitalDelayType01 := VitalZeroDelay01;
        tipd_D6             : VitalDelayType01 := VitalZeroDelay01;
        tipd_D7             : VitalDelayType01 := VitalZeroDelay01;
        tipd_D8             : VitalDelayType01 := VitalZeroDelay01;
        tipd_D9             : VitalDelayType01 := VitalZeroDelay01;
        tipd_D10            : VitalDelayType01 := VitalZeroDelay01;
        tipd_D11            : VitalDelayType01 := VitalZeroDelay01;
        tipd_D12            : VitalDelayType01 := VitalZeroDelay01;
        tipd_D13            : VitalDelayType01 := VitalZeroDelay01;
        tipd_D14            : VitalDelayType01 := VitalZeroDelay01;
        tipd_D15            : VitalDelayType01 := VitalZeroDelay01;
        tipd_A0             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A1             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A2             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A3             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A4             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A5             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A6             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A7             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A8             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A9             : VitalDelayType01 := VitalZeroDelay01;
        tipd_A10            : VitalDelayType01 := VitalZeroDelay01;
        tipd_A11            : VitalDelayType01 := VitalZeroDelay01;
        tipd_A12            : VitalDelayType01 := VitalZeroDelay01;
        tipd_A13            : VitalDelayType01 := VitalZeroDelay01;
        tipd_A14            : VitalDelayType01 := VitalZeroDelay01;
        tipd_A15            : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_BLENeg_D0                   : VitalDelayType01Z := UnitDelay01Z;
        tpd_OENeg_D0                    : VitalDelayType01Z := UnitDelay01Z;
        tpd_CENeg_D0                    : VitalDelayType01Z := UnitDelay01Z;
        tpd_A0_D0                       : VitalDelayType01  := UnitDelay01;
        -- tpw values: pulse widths
        tpw_WENeg_negedge               : VitalDelayType    := UnitDelay;
        -- tsetup values: setup times
        tsetup_BLENeg_WENeg             : VitalDelayType    := UnitDelay;
        tsetup_D0_WENeg                 : VitalDelayType    := UnitDelay;
        tsetup_D0_CENeg                 : VitalDelayType    := UnitDelay;
        -- thold values: hold times
        thold_D0_WENeg                  : VitalDelayType    := UnitDelay;
        thold_D0_CENeg                  : VitalDelayType    := UnitDelay;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXOn;
        SeverityMode        : SEVERITY_LEVEL := WARNING;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        A0              : IN    std_ulogic := 'U';
        A1              : IN    std_ulogic := 'U';
        A2              : IN    std_ulogic := 'U';
        A3              : IN    std_ulogic := 'U';
        A4              : IN    std_ulogic := 'U';
        A5              : IN    std_ulogic := 'U';
        A6              : IN    std_ulogic := 'U';
        A7              : IN    std_ulogic := 'U';
        A8              : IN    std_ulogic := 'U';
        A9              : IN    std_ulogic := 'U';
        A10             : IN    std_ulogic := 'U';
        A11             : IN    std_ulogic := 'U';
        A12             : IN    std_ulogic := 'U';
        A13             : IN    std_ulogic := 'U';
        A14             : IN    std_ulogic := 'U';
        A15             : IN    std_ulogic := 'U';
        D0              : INOUT std_ulogic := 'U';
        D1              : INOUT std_ulogic := 'U';
        D2              : INOUT std_ulogic := 'U';
        D3              : INOUT std_ulogic := 'U';
        D4              : INOUT std_ulogic := 'U';
        D5              : INOUT std_ulogic := 'U';
        D6              : INOUT std_ulogic := 'U';
        D7              : INOUT std_ulogic := 'U';
        D8              : INOUT std_ulogic := 'U';
        D9              : INOUT std_ulogic := 'U';
        D10             : INOUT std_ulogic := 'U';
        D11             : INOUT std_ulogic := 'U';
        D12             : INOUT std_ulogic := 'U';
        D13             : INOUT std_ulogic := 'U';
        D14             : INOUT std_ulogic := 'U';
        D15             : INOUT std_ulogic := 'U';
        BHENeg          : IN    std_ulogic := 'U';
        BLENeg          : IN    std_ulogic := 'U';
        OENeg           : IN    std_ulogic := 'U';
        WENeg           : IN    std_ulogic := 'U';
        CENeg           : IN    std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of idt71016 : ENTITY IS TRUE;
END idt71016;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of idt71016 IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT partID         : STRING := "IDT71016";
    CONSTANT MaxData        : NATURAL := 255;
    CONSTANT TotalLOC       : NATURAL := 65535;
    CONSTANT HiAbit         : NATURAL := 15;
    CONSTANT HiDbit         : NATURAL := 7;
    CONSTANT DataWidth      : NATURAL := 8;

    SIGNAL D0_ipd           : std_ulogic := 'U';
    SIGNAL D1_ipd           : std_ulogic := 'U';
    SIGNAL D2_ipd           : std_ulogic := 'U';
    SIGNAL D3_ipd           : std_ulogic := 'U';
    SIGNAL D4_ipd           : std_ulogic := 'U';
    SIGNAL D5_ipd           : std_ulogic := 'U';
    SIGNAL D6_ipd           : std_ulogic := 'U';
    SIGNAL D7_ipd           : std_ulogic := 'U';
    SIGNAL D8_ipd           : std_ulogic := 'U';
    SIGNAL D9_ipd           : std_ulogic := 'U';
    SIGNAL D10_ipd          : std_ulogic := 'U';
    SIGNAL D11_ipd          : std_ulogic := 'U';
    SIGNAL D12_ipd          : std_ulogic := 'U';
    SIGNAL D13_ipd          : std_ulogic := 'U';
    SIGNAL D14_ipd          : std_ulogic := 'U';
    SIGNAL D15_ipd          : std_ulogic := 'U';

    SIGNAL A0_ipd           : std_ulogic := 'U';
    SIGNAL A1_ipd           : std_ulogic := 'U';
    SIGNAL A2_ipd           : std_ulogic := 'U';
    SIGNAL A3_ipd           : std_ulogic := 'U';
    SIGNAL A4_ipd           : std_ulogic := 'U';
    SIGNAL A5_ipd           : std_ulogic := 'U';
    SIGNAL A6_ipd           : std_ulogic := 'U';
    SIGNAL A7_ipd           : std_ulogic := 'U';
    SIGNAL A8_ipd           : std_ulogic := 'U';
    SIGNAL A9_ipd           : std_ulogic := 'U';
    SIGNAL A10_ipd          : std_ulogic := 'U';
    SIGNAL A11_ipd          : std_ulogic := 'U';
    SIGNAL A12_ipd          : std_ulogic := 'U';
    SIGNAL A13_ipd          : std_ulogic := 'U';
    SIGNAL A14_ipd          : std_ulogic := 'U';
    SIGNAL A15_ipd          : std_ulogic := 'U';

    SIGNAL BHENeg_ipd       : std_ulogic := 'U';
    SIGNAL BLENeg_ipd       : std_ulogic := 'U';
    SIGNAL OENeg_ipd        : std_ulogic := 'U';
    SIGNAL WENeg_ipd        : std_ulogic := 'U';
    SIGNAL CENeg_ipd        : std_ulogic := 'U';

BEGIN
    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1: VitalWireDelay (BHENeg_ipd, BHENeg, tipd_BHENeg);
        w_2: VitalWireDelay (BLENeg_ipd, BLENeg, tipd_BLENeg);
        w_3: VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg);
        w_4: VitalWireDelay (WENeg_ipd, WENeg, tipd_WENeg);
        w_5: VitalWireDelay (CENeg_ipd, CENeg, tipd_CENeg);
        w_6: VitalWireDelay (D0_ipd, D0, tipd_D0);
        w_7: VitalWireDelay (D1_ipd, D1, tipd_D1);
        w_8: VitalWireDelay (D2_ipd, D2, tipd_D2);
        w_9: VitalWireDelay (D3_ipd, D3, tipd_D3);
        w_10: VitalWireDelay (D4_ipd, D4, tipd_D4);
        w_11: VitalWireDelay (D5_ipd, D5, tipd_D5);
        w_12: VitalWireDelay (D6_ipd, D6, tipd_D6);
        w_13: VitalWireDelay (D7_ipd, D7, tipd_D7);
        w_14: VitalWireDelay (D8_ipd, D8, tipd_D8);
        w_15: VitalWireDelay (D9_ipd, D9, tipd_D9);
        w_16: VitalWireDelay (D10_ipd, D10, tipd_D10);
        w_17: VitalWireDelay (D11_ipd, D11, tipd_D11);
        w_18: VitalWireDelay (D12_ipd, D12, tipd_D12);
        w_19: VitalWireDelay (D13_ipd, D13, tipd_D13);