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📄 mt47h64m16.vhd

📁 vhdl cod for ram.For sp3e
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        --mode registers        SHARED VARIABLE MR : std_logic_vector(12 DOWNTO 0) := (OTHERS => '0');        SHARED VARIABLE EMR : std_logic_vector(12 DOWNTO 0);        SHARED VARIABLE EMR2 : std_logic_vector(12 DOWNTO 0);        SHARED VARIABLE EMR3 : std_logic_vector(12 DOWNTO 0);        SHARED VARIABLE burst_len : natural RANGE 4 TO 8;--burst length        SHARED VARIABLE active_forbid : boolean := FALSE;--more than 4 active                                                         --commands during tFAW        --bank, row and column of scheduled read or write operation        SHARED VARIABLE current_bank : natural RANGE 0 TO BankNum;        SHARED VARIABLE current_row : natural RANGE 0 TO RowNum;        SHARED VARIABLE current_column : natural RANGE 0 TO ColNum;        --bank, row and column of read operation that starts        SHARED VARIABLE read_bank : natural RANGE 0 TO BankNum;        SHARED VARIABLE read_row : natural RANGE 0 TO RowNum;        SHARED VARIABLE read_column : natural RANGE 0 TO ColNum;        TYPE write_sch_type IS ARRAY (0 TO 10) OF boolean;        TYPE write_sch_bank_type IS ARRAY (0 TO BankNum) OF write_sch_type;        --all scheduled reads within all banks        SHARED VARIABLE read_sch : write_sch_bank_type :=                                                  (OTHERS => (OTHERS => FALSE));        --reads that should be preceeded by preamble        SHARED VARIABLE preamble : write_sch_bank_type :=                                                  (OTHERS => (OTHERS => TRUE));        TYPE wait_read_type IS ARRAY (0 TO 10) OF std_ulogic;        TYPE wait_read_bank_type IS ARRAY (0 TO BankNum) OF wait_read_type;        --wait_read triggers process that counts remaining cycles to the        --beggining of scheduled read when aditive latency has elapsed, and        --read_delay keeps information of number of remaining cycles        SIGNAL wait_read : wait_read_bank_type;        SHARED VARIABLE read_delay : natural RANGE 0 TO 7;        --needed for check if all rows were refreshed during refresh period        SIGNAL Ref_per_start : std_ulogic := '0';        SIGNAL Ref_per_expired : std_ulogic := '0';        SHARED VARIABLE CK_rise : time := 0 ns;        SHARED VARIABLE CK_period : time := 0 ns;        TYPE Bank_state_type IS (precharged, refreshing, MRsetting, activating,                                 active, reading, readingAP, writting,                                 writtingAP, precharging, prechall);        TYPE Bank_state_array_type IS ARRAY (0 TO BankNum) OF Bank_state_type;        SHARED VARIABLE Curr_bank_state : Bank_state_array_type;        SHARED VARIABLE Next_bank_state : Bank_state_array_type;        SHARED VARIABLE SR_cond : boolean := FALSE;--self refresh can be entered        SIGNAL SelfRefresh : boolean := FALSE;--self refresh active        SIGNAL SR_exit : boolean := FALSE;--CKE high, self refresh exit        SHARED VARIABLE SR_enter_cycle : boolean := FALSE;--clock can be                                                          --turned off        SIGNAL Pre_PD : boolean := FALSE;--precharge power down active        SIGNAL Act_PD : boolean := FALSE;--active power down active        SHARED VARIABLE Read_Start : boolean := FALSE;--read burst in progress,        SIGNAL ReadStart : boolean := FALSE;          --no pd entry        SIGNAL Reset : boolean := FALSE;--reset function active        SHARED VARIABLE Reset_enter_cycle : boolean := FALSE;--clocks can be                                                             --turned off        SIGNAL SimulationEnd : boolean := FALSE;        SIGNAL preamble_check : boolean := FALSE;        SIGNAL postamble_check : boolean := FALSE;        SIGNAL skew_check : boolean := FALSE;        FUNCTION bool_to_nat(tm : boolean)        RETURN natural IS            VARIABLE Temp : natural;        BEGIN            Temp := 0;            IF tm THEN                Temp := 1;            END IF;            RETURN Temp;        END bool_to_nat;    BEGIN    CK_DLL: PROCESS(CKDiff)        VARIABLE Previous : time := 0 ns;        VARIABLE TmpPer : time := 0 ns;    BEGIN        IF rising_edge(CKDiff) THEN            TmpPer := NOW - Previous;            IF TmpPer > 0 ns THEN                CKPeriod <= TmpPer;            END IF;            Previous := NOW;            CKHalfPer <= CKPeriod / 2;            CKDLLDelay <= CKPeriod - tpd_CK_DQ1;        END IF;    END PROCESS CK_DLL;    CK_temp: PROCESS(CKDiff) -- generating internal clock from DLL    BEGIN        CKtemp <= NOT CKDiff AFTER CKHalfPer;    END PROCESS CK_temp;    CKInt <= TRANSPORT CKtemp AFTER CKDLLDelay;    Power_up: PROCESS(CK_stable)    BEGIN        IF CK_stable THEN            PoweredUp <= TRUE AFTER 200 us;        END IF;    END PROCESS Power_up;    Init_d: PROCESS(In_d)    BEGIN        IF In_d THEN            Init_delay <= TRUE AFTER 400 ns;        ELSE            Init_delay <= FALSE;        END IF;    END PROCESS Init_d;    DLLdelay: PROCESS(DLL_delay, CKDiff)        VARIABLE cnt : natural;    BEGIN        IF rising_edge(DLL_delay) THEN            cnt := 0;            DLL_delay_elapsed <= FALSE;        ELSIF rising_edge(CKDiff) AND NOT DLL_delay_elapsed THEN            cnt := cnt + 1;            IF cnt = 199 THEN                DLL_delay_elapsed <= TRUE;            END IF;        END IF;    END PROCESS DLLdelay;    ----------------------------------------------------------------------------    -- Main Behavior Process    ----------------------------------------------------------------------------    VITALBehaviour: PROCESS(CKDiff, LDQSDiff, LDQSIn, UDQSDiff, UDQSIn, DQIn_Lo,                            DQIn_Hi, LDM, UDM, ODT, CKE, CSNeg, RASNeg, CASNeg,                            WENeg, BAIn, AIn)        -- Timing Check Variables        VARIABLE Tviol_DQ0_LDQS    : X01 := '0';        VARIABLE TD_DQ0_LDQS       : VitalTimingDataType;        VARIABLE Tviol_DQ0_LDQS1   : X01 := '0';        VARIABLE TD_DQ0_LDQS1      : VitalTimingDataType;        VARIABLE Tviol_DQ1_LDQS    : X01 := '0';        VARIABLE TD_DQ1_LDQS       : VitalTimingDataType;        VARIABLE Tviol_DQ1_LDQS1   : X01 := '0';        VARIABLE TD_DQ1_LDQS1      : VitalTimingDataType;        VARIABLE Tviol_DQ0_UDQS    : X01 := '0';        VARIABLE TD_DQ0_UDQS       : VitalTimingDataType;        VARIABLE Tviol_DQ0_UDQS1   : X01 := '0';        VARIABLE TD_DQ0_UDQS1      : VitalTimingDataType;        VARIABLE Tviol_DQ1_UDQS    : X01 := '0';        VARIABLE TD_DQ1_UDQS       : VitalTimingDataType;        VARIABLE Tviol_DQ1_UDQS1   : X01 := '0';        VARIABLE TD_DQ1_UDQS1      : VitalTimingDataType;        VARIABLE Tviol_LDM0_LDQS   : X01 := '0';        VARIABLE TD_LDM0_LDQS      : VitalTimingDataType;        VARIABLE Tviol_LDM0_LDQS1  : X01 := '0';        VARIABLE TD_LDM0_LDQS1     : VitalTimingDataType;        VARIABLE Tviol_LDM1_LDQS   : X01 := '0';        VARIABLE TD_LDM1_LDQS      : VitalTimingDataType;        VARIABLE Tviol_LDM1_LDQS1  : X01 := '0';        VARIABLE TD_LDM1_LDQS1     : VitalTimingDataType;        VARIABLE Tviol_UDM0_UDQS   : X01 := '0';        VARIABLE TD_UDM0_UDQS      : VitalTimingDataType;        VARIABLE Tviol_UDM0_UDQS1  : X01 := '0';        VARIABLE TD_UDM0_UDQS1     : VitalTimingDataType;        VARIABLE Tviol_UDM1_UDQS   : X01 := '0';        VARIABLE TD_UDM1_UDQS      : VitalTimingDataType;        VARIABLE Tviol_UDM1_UDQS1  : X01 := '0';        VARIABLE TD_UDM1_UDQS1     : VitalTimingDataType;        VARIABLE Tviol_ODT_CK      : X01 := '0';        VARIABLE TD_ODT_CK         : VitalTimingDataType;        VARIABLE Tviol_CKE_CK      : X01 := '0';        VARIABLE TD_CKE_CK         : VitalTimingDataType;        VARIABLE Tviol_CSNeg_CK    : X01 := '0';        VARIABLE TD_CSNeg_CK       : VitalTimingDataType;        VARIABLE Tviol_RASNeg_CK   : X01 := '0';        VARIABLE TD_RASNeg_CK      : VitalTimingDataType;        VARIABLE Tviol_CASNeg_CK   : X01 := '0';        VARIABLE TD_CASNeg_CK      : VitalTimingDataType;        VARIABLE Tviol_WENeg_CK    : X01 := '0';        VARIABLE TD_WENeg_CK       : VitalTimingDataType;        VARIABLE Tviol_BA0_CK      : X01 := '0';        VARIABLE TD_BA0_CK         : VitalTimingDataType;        VARIABLE Tviol_A0_CK       : X01 := '0';        VARIABLE TD_A0_CK          : VitalTimingDataType;        VARIABLE Tviol_LDQS_CK3    : X01 := '0';        VARIABLE TD_LDQS_CK3       : VitalTimingDataType;        VARIABLE Tviol_LDQS_CK4    : X01 := '0';        VARIABLE TD_LDQS_CK4       : VitalTimingDataType;        VARIABLE Tviol_LDQS_CK5    : X01 := '0';        VARIABLE TD_LDQS_CK5       : VitalTimingDataType;        VARIABLE Tviol_LDQS_CK6    : X01 := '0';        VARIABLE TD_LDQS_CK6       : VitalTimingDataType;        VARIABLE Tviol_LDQS1_CK3   : X01 := '0';        VARIABLE TD_LDQS1_CK3      : VitalTimingDataType;        VARIABLE Tviol_LDQS1_CK4   : X01 := '0';        VARIABLE TD_LDQS1_CK4      : VitalTimingDataType;        VARIABLE Tviol_LDQS1_CK5   : X01 := '0';        VARIABLE TD_LDQS1_CK5      : VitalTimingDataType;        VARIABLE Tviol_LDQS1_CK6   : X01 := '0';        VARIABLE TD_LDQS1_CK6      : VitalTimingDataType;        VARIABLE Tviol_UDQS_CK3    : X01 := '0';        VARIABLE TD_UDQS_CK3       : VitalTimingDataType;        VARIABLE Tviol_UDQS_CK4    : X01 := '0';        VARIABLE TD_UDQS_CK4       : VitalTimingDataType;        VARIABLE Tviol_UDQS_CK5    : X01 := '0';        VARIABLE TD_UDQS_CK5       : VitalTimingDataType;        VARIABLE Tviol_UDQS_CK6    : X01 := '0';        VARIABLE TD_UDQS_CK6       : VitalTimingDataType;        VARIABLE Tviol_UDQS1_CK3   : X01 := '0';        VARIABLE TD_UDQS1_CK3      : VitalTimingDataType;        VARIABLE Tviol_UDQS1_CK4   : X01 := '0';        VARIABLE TD_UDQS1_CK4      : VitalTimingDataType;        VARIABLE Tviol_UDQS1_CK5   : X01 := '0';        VARIABLE TD_UDQS1_CK5      : VitalTimingDataType;        VARIABLE Tviol_UDQS1_CK6   : X01 := '0';        VARIABLE TD_UDQS1_CK6      : VitalTimingDataType;

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