📄 mt47h64m16.vhd
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SIGNAL A3_ipd : std_ulogic := 'U'; SIGNAL A4_ipd : std_ulogic := 'U'; SIGNAL A5_ipd : std_ulogic := 'U'; SIGNAL A6_ipd : std_ulogic := 'U'; SIGNAL A7_ipd : std_ulogic := 'U'; SIGNAL A8_ipd : std_ulogic := 'U'; SIGNAL A9_ipd : std_ulogic := 'U'; SIGNAL A10_ipd : std_ulogic := 'U'; SIGNAL A11_ipd : std_ulogic := 'U'; SIGNAL A12_ipd : std_ulogic := 'U'; SIGNAL DQ0_ipd : std_ulogic := 'U'; SIGNAL DQ1_ipd : std_ulogic := 'U'; SIGNAL DQ2_ipd : std_ulogic := 'U'; SIGNAL DQ3_ipd : std_ulogic := 'U'; SIGNAL DQ4_ipd : std_ulogic := 'U'; SIGNAL DQ5_ipd : std_ulogic := 'U'; SIGNAL DQ6_ipd : std_ulogic := 'U'; SIGNAL DQ7_ipd : std_ulogic := 'U'; SIGNAL DQ8_ipd : std_ulogic := 'U'; SIGNAL DQ9_ipd : std_ulogic := 'U'; SIGNAL DQ10_ipd : std_ulogic := 'U'; SIGNAL DQ11_ipd : std_ulogic := 'U'; SIGNAL DQ12_ipd : std_ulogic := 'U'; SIGNAL DQ13_ipd : std_ulogic := 'U'; SIGNAL DQ14_ipd : std_ulogic := 'U'; SIGNAL DQ15_ipd : std_ulogic := 'U'; SIGNAL UDQS_ipd : std_ulogic := 'U'; SIGNAL UDQSNeg_ipd : std_ulogic := 'U'; SIGNAL LDQS_ipd : std_ulogic := 'U'; SIGNAL LDQSNeg_ipd : std_ulogic := 'U'; -- nwv SIGNAL ODT_nwv : std_ulogic := 'U'; SIGNAL CK_nwv : std_ulogic := 'U'; SIGNAL CKNeg_nwv : std_ulogic := 'U'; SIGNAL CKE_nwv : std_ulogic := 'U'; SIGNAL CSNeg_nwv : std_ulogic := 'U'; SIGNAL RASNeg_nwv : std_ulogic := 'U'; SIGNAL CASNeg_nwv : std_ulogic := 'U'; SIGNAL WENeg_nwv : std_ulogic := 'U'; SIGNAL LDM_nwv : std_ulogic := 'U'; SIGNAL UDM_nwv : std_ulogic := 'U'; SIGNAL BA0_nwv : std_ulogic := 'U'; SIGNAL BA1_nwv : std_ulogic := 'U'; SIGNAL BA2_nwv : std_ulogic := 'U'; SIGNAL A0_nwv : std_ulogic := 'U'; SIGNAL A1_nwv : std_ulogic := 'U'; SIGNAL A2_nwv : std_ulogic := 'U'; SIGNAL A3_nwv : std_ulogic := 'U'; SIGNAL A4_nwv : std_ulogic := 'U'; SIGNAL A5_nwv : std_ulogic := 'U'; SIGNAL A6_nwv : std_ulogic := 'U'; SIGNAL A7_nwv : std_ulogic := 'U'; SIGNAL A8_nwv : std_ulogic := 'U'; SIGNAL A9_nwv : std_ulogic := 'U'; SIGNAL A10_nwv : std_ulogic := 'U'; SIGNAL A11_nwv : std_ulogic := 'U'; SIGNAL A12_nwv : std_ulogic := 'U'; SIGNAL DQ0_nwv : std_ulogic := 'U'; SIGNAL DQ1_nwv : std_ulogic := 'U'; SIGNAL DQ2_nwv : std_ulogic := 'U'; SIGNAL DQ3_nwv : std_ulogic := 'U'; SIGNAL DQ4_nwv : std_ulogic := 'U'; SIGNAL DQ5_nwv : std_ulogic := 'U'; SIGNAL DQ6_nwv : std_ulogic := 'U'; SIGNAL DQ7_nwv : std_ulogic := 'U'; SIGNAL DQ8_nwv : std_ulogic := 'U'; SIGNAL DQ9_nwv : std_ulogic := 'U'; SIGNAL DQ10_nwv : std_ulogic := 'U'; SIGNAL DQ11_nwv : std_ulogic := 'U'; SIGNAL DQ12_nwv : std_ulogic := 'U'; SIGNAL DQ13_nwv : std_ulogic := 'U'; SIGNAL DQ14_nwv : std_ulogic := 'U'; SIGNAL DQ15_nwv : std_ulogic := 'U'; SIGNAL UDQS_nwv : std_ulogic := 'U'; SIGNAL UDQSNeg_nwv : std_ulogic := 'U'; SIGNAL LDQS_nwv : std_ulogic := 'U'; SIGNAL LDQSNeg_nwv : std_ulogic := 'U'; --- internal delays SIGNAL tRC_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tRC_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tRRD_in : std_ulogic := '1'; SIGNAL tRRD_out : std_ulogic := '1'; SIGNAL tRCD_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tRCD_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tFAW_in : std_ulogic_vector(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL tFAW_out : std_ulogic_vector(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL tRASMIN_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tRASMIN_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tRASMAX_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tRASMAX_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tRTP_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tRTP_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tWR_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tWR_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tWTR_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tWTR_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tRP_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tRP_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tRFCMIN_in : std_ulogic := '0'; SIGNAL tRFCMIN_out : std_ulogic := '0'; SIGNAL tRFCMAX_in : std_ulogic := '0'; SIGNAL tRFCMAX_out : std_ulogic := '0'; SIGNAL tXSNR_in : std_ulogic := '0'; SIGNAL tXSNR_out : std_ulogic := '0'; SIGNAL REFPer_in : std_ulogic := '0'; SIGNAL REFPer_out : std_ulogic := '0'; SIGNAL tCKAVGMAX_in : std_ulogic := '0'; SIGNAL tCKAVGMAX_out : std_ulogic := '0'; SIGNAL tWPSTMAX_in : std_ulogic := '0'; SIGNAL tWPSTMAX_out : std_ulogic := '0';BEGIN ---------------------------------------------------------------------------- -- Internal Delays ---------------------------------------------------------------------------- TRC : VitalBuf(tRC_out(0), tRC_in(0), (tdevice_tRC - 1 ns, UnitDelay)); TRC1 : VitalBuf(tRC_out(1), tRC_in(1), (tdevice_tRC - 1 ns, UnitDelay)); TRC2 : VitalBuf(tRC_out(2), tRC_in(2), (tdevice_tRC - 1 ns, UnitDelay)); TRC3 : VitalBuf(tRC_out(3), tRC_in(3), (tdevice_tRC - 1 ns, UnitDelay)); TRC4 : VitalBuf(tRC_out(4), tRC_in(4), (tdevice_tRC - 1 ns, UnitDelay)); TRC5 : VitalBuf(tRC_out(5), tRC_in(5), (tdevice_tRC - 1 ns, UnitDelay)); TRC6 : VitalBuf(tRC_out(6), tRC_in(6), (tdevice_tRC - 1 ns, UnitDelay)); TRC7 : VitalBuf(tRC_out(7), tRC_in(7), (tdevice_tRC - 1 ns, UnitDelay)); TRRD : VitalBuf(tRRD_out, tRRD_in, (tdevice_tRRD - 1 ns, UnitDelay)); TRCD : VitalBuf(tRCD_out(0), tRCD_in(0), (tdevice_tRCD - 1 ns, UnitDelay)); TRCD1 : VitalBuf(tRCD_out(1), tRCD_in(1), (tdevice_tRCD - 1 ns, UnitDelay)); TRCD2 : VitalBuf(tRCD_out(2), tRCD_in(2), (tdevice_tRCD - 1 ns, UnitDelay)); TRCD3 : VitalBuf(tRCD_out(3), tRCD_in(3), (tdevice_tRCD - 1 ns, UnitDelay)); TRCD4 : VitalBuf(tRCD_out(4), tRCD_in(4), (tdevice_tRCD - 1 ns, UnitDelay)); TRCD5 : VitalBuf(tRCD_out(5), tRCD_in(5), (tdevice_tRCD - 1 ns, UnitDelay)); TRCD6 : VitalBuf(tRCD_out(6), tRCD_in(6), (tdevice_tRCD - 1 ns, UnitDelay)); TRCD7 : VitalBuf(tRCD_out(7), tRCD_in(7), (tdevice_tRCD - 1 ns, UnitDelay)); TFAW : VitalBuf(tFAW_out(0), tFAW_in(0), (tdevice_tFAW - 2 ns, UnitDelay)); TFAW1 : VitalBuf(tFAW_out(1), tFAW_in(1), (tdevice_tFAW - 2 ns, UnitDelay)); TFAW2 : VitalBuf(tFAW_out(2), tFAW_in(2), (tdevice_tFAW - 2 ns, UnitDelay)); TFAW3 : VitalBuf(tFAW_out(3), tFAW_in(3), (tdevice_tFAW - 2 ns, UnitDelay)); TRASMIN : VitalBuf(tRASMIN_out(0), tRASMIN_in(0), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMIN1 : VitalBuf(tRASMIN_out(1), tRASMIN_in(1), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMIN2 : VitalBuf(tRASMIN_out(2), tRASMIN_in(2), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMIN3 : VitalBuf(tRASMIN_out(3), tRASMIN_in(3), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMIN4 : VitalBuf(tRASMIN_out(4), tRASMIN_in(4), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMIN5 : VitalBuf(tRASMIN_out(5), tRASMIN_in(5), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMIN6 : VitalBuf(tRASMIN_out(6), tRASMIN_in(6), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMIN7 : VitalBuf(tRASMIN_out(7), tRASMIN_in(7), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMAX : VitalBuf(tRASMAX_out(0), tRASMAX_in(0), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRASMAX1 : VitalBuf(tRASMAX_out(1), tRASMAX_in(1), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRASMAX2 : VitalBuf(tRASMAX_out(2), tRASMAX_in(2), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRASMAX3 : VitalBuf(tRASMAX_out(3), tRASMAX_in(3), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRASMAX4 : VitalBuf(tRASMAX_out(4), tRASMAX_in(4), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRASMAX5 : VitalBuf(tRASMAX_out(5), tRASMAX_in(5), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRASMAX6 : VitalBuf(tRASMAX_out(6), tRASMAX_in(6), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRASMAX7 : VitalBuf(tRASMAX_out(7), tRASMAX_in(7), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRTP : VitalBuf(tRTP_out(0), tRTP_in(0), (tdevice_tRTP - 1 ns, UnitDelay)); TRTP1 : VitalBuf(tRTP_out(1), tRTP_in(1), (tdevice_tRTP - 1 ns, UnitDelay)); TRTP2 : VitalBuf(tRTP_out(2), tRTP_in(2), (tdevice_tRTP - 1 ns, UnitDelay)); TRTP3 : VitalBuf(tRTP_out(3), tRTP_in(3), (tdevice_tRTP - 1 ns, UnitDelay)); TRTP4 : VitalBuf(tRTP_out(4), tRTP_in(4), (tdevice_tRTP - 1 ns, UnitDelay)); TRTP5 : VitalBuf(tRTP_out(5), tRTP_in(5), (tdevice_tRTP - 1 ns, UnitDelay)); TRTP6 : VitalBuf(tRTP_out(6), tRTP_in(6), (tdevice_tRTP - 1 ns, UnitDelay)); TRTP7 : VitalBuf(tRTP_out(7), tRTP_in(7), (tdevice_tRTP - 1 ns, UnitDelay)); TWR : VitalBuf(tWR_out(0), tWR_in(0), (tdevice_tWR - 1 ns, UnitDelay)); TWR1 : VitalBuf(tWR_out(1), tWR_in(1), (tdevice_tWR - 1 ns, UnitDelay)); TWR2 : VitalBuf(tWR_out(2), tWR_in(2), (tdevice_tWR - 1 ns, UnitDelay)); TWR3 : VitalBuf(tWR_out(3), tWR_in(3), (tdevice_tWR - 1 ns, UnitDelay)); TWR4 : VitalBuf(tWR_out(4), tWR_in(4), (tdevice_tWR - 1 ns, UnitDelay)); TWR5 : VitalBuf(tWR_out(5), tWR_in(5), (tdevice_tWR - 1 ns, UnitDelay)); TWR6 : VitalBuf(tWR_out(6), tWR_in(6), (tdevice_tWR - 1 ns, UnitDelay)); TWR7 : VitalBuf(tWR_out(7), tWR_in(7), (tdevice_tWR - 1 ns, UnitDelay)); TWTR : VitalBuf(tWTR_out(0), tWTR_in(0), (tdevice_tWTR - 1 ns, UnitDelay)); TWTR1 : VitalBuf(tWTR_out(1), tWTR_in(1), (tdevice_tWTR - 1 ns, UnitDelay)); TWTR2 : VitalBuf(tWTR_out(2), tWTR_in(2), (tdevice_tWTR - 1 ns, UnitDelay)); TWTR3 : VitalBuf(tWTR_out(3), tWTR_in(3), (tdevice_tWTR - 1 ns, UnitDelay)); TWTR4 : VitalBuf(tWTR_out(4), tWTR_in(4), (tdevice_tWTR - 1 ns, UnitDelay)); TWTR5 : VitalBuf(tWTR_out(5), tWTR_in(5), (tdevice_tWTR - 1 ns, UnitDelay)); TWTR6 : VitalBuf(tWTR_out(6), tWTR_in(6), (tdevice_tWTR - 1 ns, UnitDelay)); TWTR7 : VitalBuf(tWTR_out(7), tWTR_in(7), (tdevice_tWTR - 1 ns, UnitDelay)); TRP : VitalBuf(tRP_out(0), tRP_in(0), (tdevice_tRP - 1 ns, UnitDelay)); TRP1 : VitalBuf(tRP_out(1), tRP_in(1), (tdevice_tRP - 1 ns, UnitDelay)); TRP2 : VitalBuf(tRP_out(2), tRP_in(2), (tdevice_tRP - 1 ns, UnitDelay)); TRP3 : VitalBuf(tRP_out(3), tRP_in(3), (tdevice_tRP - 1 ns, UnitDelay)); TRP4 : VitalBuf(tRP_out(4), tRP_in(4), (tdevice_tRP - 1 ns, UnitDelay)); TRP5 : VitalBuf(tRP_out(5), tRP_in(5), (tdevice_tRP - 1 ns, UnitDelay)); TRP6 : VitalBuf(tRP_out(6), tRP_in(6), (tdevice_tRP - 1 ns, UnitDelay)); TRP7 : VitalBuf(tRP_out(7), tRP_in(7), (tdevice_tRP - 1 ns, UnitDelay)); TRFCMIN : VitalBuf(tRFCMIN_out, tRFCMIN_in, (tdevice_tRFCMIN - 1 ns, UnitDelay)); TRFCMAX : VitalBuf(tRFCMAX_out, tRFCMAX_in, (tdevice_tRFCMAX - 1 ns, UnitDelay)); TXSNR : VitalBuf(tXSNR_out, tXSNR_in, (tdevice_tRFCMIN + 9 ns, UnitDelay)); REFPER : VitalBuf(REFPer_out, REFPer_in, (tdevice_REFPer - 1 ns, UnitDelay)); TCKAVGMAX: VitalBuf(tCKAVGMAX_out, tCKAVGMAX_in, (tdevice_tCKAVGMAX - 1 ns, UnitDelay));
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