edj1308ba.vhd

vhdl cod for ram.For sp3e

    TRTP3    : VitalBuf(tRTP_out(3), tRTP_in(3), (tdevice_tRTP - 1 ns,
                                                                    UnitDelay));
    TRTP4    : VitalBuf(tRTP_out(4), tRTP_in(4), (tdevice_tRTP - 1 ns,
                                                                    UnitDelay));
    TRTP5    : VitalBuf(tRTP_out(5), tRTP_in(5), (tdevice_tRTP - 1 ns,
                                                                    UnitDelay));
    TRTP6    : VitalBuf(tRTP_out(6), tRTP_in(6), (tdevice_tRTP - 1 ns,
                                                                    UnitDelay));
    TRTP7    : VitalBuf(tRTP_out(7), tRTP_in(7), (tdevice_tRTP - 1 ns,
                                                                    UnitDelay));
    TWR      : VitalBuf(tWR_out(0), tWR_in(0), (tdevice_tWR - 1 ns,
                                                                    UnitDelay));
    TWR1     : VitalBuf(tWR_out(1), tWR_in(1), (tdevice_tWR - 1 ns,
                                                                    UnitDelay));
    TWR2     : VitalBuf(tWR_out(2), tWR_in(2), (tdevice_tWR - 1 ns,
                                                                    UnitDelay));
    TWR3     : VitalBuf(tWR_out(3), tWR_in(3), (tdevice_tWR - 1 ns,
                                                                    UnitDelay));
    TWR4     : VitalBuf(tWR_out(4), tWR_in(4), (tdevice_tWR - 1 ns,
                                                                    UnitDelay));
    TWR5     : VitalBuf(tWR_out(5), tWR_in(5), (tdevice_tWR - 1 ns,
                                                                    UnitDelay));
    TWR6     : VitalBuf(tWR_out(6), tWR_in(6), (tdevice_tWR - 1 ns,
                                                                    UnitDelay));
    TWR7     : VitalBuf(tWR_out(7), tWR_in(7), (tdevice_tWR - 1 ns,
                                                                    UnitDelay));
    TWTR     : VitalBuf(tWTR_out(0), tWTR_in(0), (tdevice_tWTR - 1 ns,
                                                                    UnitDelay));
    TWTR1    : VitalBuf(tWTR_out(1), tWTR_in(1), (tdevice_tWTR - 1 ns,
                                                                    UnitDelay));
    TWTR2    : VitalBuf(tWTR_out(2), tWTR_in(2), (tdevice_tWTR - 1 ns,
                                                                    UnitDelay));
    TWTR3    : VitalBuf(tWTR_out(3), tWTR_in(3), (tdevice_tWTR - 1 ns,
                                                                    UnitDelay));
    TWTR4    : VitalBuf(tWTR_out(4), tWTR_in(4), (tdevice_tWTR - 1 ns,
                                                                    UnitDelay));
    TWTR5    : VitalBuf(tWTR_out(5), tWTR_in(5), (tdevice_tWTR - 1 ns,
                                                                    UnitDelay));
    TWTR6    : VitalBuf(tWTR_out(6), tWTR_in(6), (tdevice_tWTR - 1 ns,
                                                                    UnitDelay));
    TWTR7    : VitalBuf(tWTR_out(7), tWTR_in(7), (tdevice_tWTR - 1 ns,
                                                                    UnitDelay));
    TRP      : VitalBuf(tRP_out(0), tRP_in(0), (tdevice_tRP - 1 ns,
                                                                    UnitDelay));
    TRP1     : VitalBuf(tRP_out(1), tRP_in(1), (tdevice_tRP - 1 ns,
                                                                    UnitDelay));
    TRP2     : VitalBuf(tRP_out(2), tRP_in(2), (tdevice_tRP - 1 ns,
                                                                    UnitDelay));
    TRP3     : VitalBuf(tRP_out(3), tRP_in(3), (tdevice_tRP - 1 ns,
                                                                    UnitDelay));
    TRP4     : VitalBuf(tRP_out(4), tRP_in(4), (tdevice_tRP - 1 ns,
                                                                    UnitDelay));
    TRP5     : VitalBuf(tRP_out(5), tRP_in(5), (tdevice_tRP - 1 ns,
                                                                    UnitDelay));
    TRP6     : VitalBuf(tRP_out(6), tRP_in(6), (tdevice_tRP - 1 ns,
                                                                    UnitDelay));
    TRP7     : VitalBuf(tRP_out(7), tRP_in(7), (tdevice_tRP - 1 ns,
                                                                    UnitDelay));
    TCKESR      : VitalBuf(tCKESR_out(0), tCKESR_in(0), (tdevice_tCKESR - 1 ns,
                                                                    UnitDelay));
    TCKESR1     : VitalBuf(tCKESR_out(1), tCKESR_in(1), (tdevice_tCKESR - 1 ns,
                                                                    UnitDelay));
    TCKESR2     : VitalBuf(tCKESR_out(2), tCKESR_in(2), (tdevice_tCKESR - 1 ns,
                                                                    UnitDelay));
    TCKESR3     : VitalBuf(tCKESR_out(3), tCKESR_in(3), (tdevice_tCKESR - 1 ns,
                                                                    UnitDelay));
    TCKESR4     : VitalBuf(tCKESR_out(4), tCKESR_in(4), (tdevice_tCKESR - 1 ns,
                                                                    UnitDelay));
    TCKESR5     : VitalBuf(tCKESR_out(5), tCKESR_in(5), (tdevice_tCKESR - 1 ns,
                                                                    UnitDelay));
    TCKESR6     : VitalBuf(tCKESR_out(6), tCKESR_in(6), (tdevice_tCKESR - 1 ns,
                                                                    UnitDelay));
    TCKESR7     : VitalBuf(tCKESR_out(7), tCKESR_in(7), (tdevice_tCKESR - 1 ns,
                                                                    UnitDelay));
    TRFCMIN  : VitalBuf(tRFCMIN_out, tRFCMIN_in, (tdevice_tRFCMIN - 1 ns,
                                                                    UnitDelay));
    TXS    : VitalBuf(tXS_out,   tXS_in,   (tdevice_tRFCMIN + 9 ns,
                                                                    UnitDelay));
    TREFPER   : VitalBuf(tREFPer_out,  tREFPer_in,  (tdevice_tREFPer - 1 ns,
                                                                    UnitDelay));
    TCKAVGMAX: VitalBuf(tCKAVGMAX_out, tCKAVGMAX_in, (tdevice_tCKAVGMAX - 1 ns,
                                                                    UnitDelay));
    TMRD: VitalBuf(tMRD_out, tMRD_in, (tdevice_tMRD - 1 ns,
                                                                    UnitDelay));
    TMOD: VitalBuf(tMOD_out, tMOD_in, (tdevice_tMOD - 1 ns,
                                                                    UnitDelay));
    TXPR: VitalBuf(tXPR_out, tXPR_in, (tdevice_tXPR - 1 ns,
                                                                    UnitDelay));
    TZQINIT: VitalBuf(tZQINIT_out, tZQINIT_in, (tdevice_tZQINIT - 1 ns,
                                                                    UnitDelay));
    TZQOPER: VitalBuf(tZQOPER_out, tZQOPER_in, (tdevice_tZQOPER - 1 ns,
                                                                    UnitDelay));
    TZQCS: VitalBuf(tZQCS_out, tZQCS_in, (tdevice_tZQCS - 1 ns,
                                                                    UnitDelay));
    TCKSRX   : VitalBuf(tCKSRX_out, tCKSRX_in, (tdevice_tCKSRX - 1 ns,
                                                                    UnitDelay));
    TCKSRE   : VitalBuf(tCKSRE_out, tCKSRE_in, (tdevice_tCKSRE - 1 ns,
                                                                    UnitDelay));
    TWLODTEN : VitalBuf(tWLODTEN_out, tWLODTEN_in, (tdevice_tMOD -1 ns,
                                                                    UnitDelay));
    TWLDQSEN : VitalBuf(tWLDQSEN_out,  tWLDQSEN_in,(tdevice_tWLDQSEN - 1 ns,
                                                                    UnitDelay));
    TWLMRD   : VitalBuf(tWLMRD_out, tWLMRD_in, (tdevice_tWLMRD - 1 ns,
                                                                    UnitDelay));
    TWLOMAX  : VitalBuf(tWLOMAX_out, tWLOMAX_in, (tdevice_tWLOMAX - 1 ns,
                                                                    UnitDelay));
    TWLOEMAX : VitalBuf(tWLOEMAX_out, tWLOEMAX_in, (tdevice_tWLOEMAX - 1 ns,
                                                                    UnitDelay));
    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN
        w_01 : VitalWireDelay (ODT_ipd, ODT, tipd_ODT);
        w_02 : VitalWireDelay (CK_ipd, CK, tipd_CK);
        w_03 : VitalWireDelay (CKNeg_ipd, CKNeg, tipd_CKNeg);
        w_04 : VitalWireDelay (CKE_ipd, CKE, tipd_CKE);
        w_05 : VitalWireDelay (CSNeg_ipd, CSNeg, tipd_CSNeg);
        w_06 : VitalWireDelay (RASNeg_ipd, RASNeg, tipd_RASNeg);
        w_07 : VitalWireDelay (CASNeg_ipd, CASNeg, tipd_CASNeg);
        w_08 : VitalWireDelay (WENeg_ipd, WENeg, tipd_WENeg);
        w_09 : VitalWireDelay (BA0_ipd, BA0, tipd_BA0);
        w_10 : VitalWireDelay (BA1_ipd, BA1, tipd_BA1);
        w_11 : VitalWireDelay (BA2_ipd, BA2, tipd_BA2);
        w_12 : VitalWireDelay (A0_ipd, A0, tipd_A0);
        w_13 : VitalWireDelay (A1_ipd, A1, tipd_A1);
        w_14 : VitalWireDelay (A2_ipd, A2, tipd_A2);
        w_15 : VitalWireDelay (A3_ipd, A3, tipd_A3);
        w_16 : VitalWireDelay (A4_ipd, A4, tipd_A4);
        w_17 : VitalWireDelay (A5_ipd, A5, tipd_A5);
        w_18 : VitalWireDelay (A6_ipd, A6, tipd_A6);
        w_19 : VitalWireDelay (A7_ipd, A7, tipd_A7);
        w_20 : VitalWireDelay (A8_ipd, A8, tipd_A8);
        w_21 : VitalWireDelay (A9_ipd, A9, tipd_A9);
        w_22 : VitalWireDelay (A10_ipd, A10, tipd_A10);
        w_23 : VitalWireDelay (A11_ipd, A11, tipd_A11);
        w_24 : VitalWireDelay (A12_ipd, A12, tipd_A12);
        w_25 : VitalWireDelay (A13_ipd, A13, tipd_A13);
        w_26 : VitalWireDelay (DQ0_ipd, DQ0, tipd_DQ0);
        w_27 : VitalWireDelay (DQ1_ipd, DQ1, tipd_DQ1);
        w_28 : VitalWireDelay (DQ2_ipd, DQ2, tipd_DQ2);
        w_29 : VitalWireDelay (DQ3_ipd, DQ3, tipd_DQ3);
        w_30 : VitalWireDelay (DQ4_ipd, DQ4, tipd_DQ4);
        w_31 : VitalWireDelay (DQ5_ipd, DQ5, tipd_DQ5);
        w_32 : VitalWireDelay (DQ6_ipd, DQ6, tipd_DQ6);
        w_33 : VitalWireDelay (DQ7_ipd, DQ7, tipd_DQ7);
        w_34 : VitalWireDelay (DQS_ipd, DQS, tipd_DQS);
        w_35 : VitalWireDelay (DQSNeg_ipd, DQSNeg, tipd_DQSNeg);
        w_36 : VitalWireDelay (RESETNeg_ipd, RESETNeg, tipd_RESETNeg);
        w_37 : VitalWireDelay (TDQS_ipd, TDQS, tipd_TDQS);
        w_38 : VitalWireDelay (TDQSNeg_ipd, TDQSNeg, tipd_TDQSNeg);

    END BLOCK;

    ODT_nwv        <= To_UX01(ODT_ipd);
    CK_nwv         <= To_UX01(CK_ipd);
    CKNeg_nwv      <= To_UX01(CKNeg_ipd);
    CKE_nwv        <= To_UX01(CKE_ipd);
    CSNeg_nwv      <= To_UX01(CSNeg_ipd);
    RASNeg_nwv     <= To_UX01(RASNeg_ipd);
    CASNeg_nwv     <= To_UX01(CASNeg_ipd);
    WENeg_nwv      <= To_UX01(WENeg_ipd);
    BA0_nwv        <= To_UX01(BA0_ipd);
    BA1_nwv        <= To_UX01(BA1_ipd);
    BA2_nwv        <= To_UX01(BA2_ipd);
    A0_nwv         <= To_UX01(A0_ipd);
    A1_nwv         <= To_UX01(A1_ipd);
    A2_nwv         <= To_UX01(A2_ipd);
    A3_nwv         <= To_UX01(A3_ipd);
    A4_nwv         <= To_UX01(A4_ipd);
    A5_nwv         <= To_UX01(A5_ipd);
    A6_nwv         <= To_UX01(A6_ipd);
    A7_nwv         <= To_UX01(A7_ipd);
    A8_nwv         <= To_UX01(A8_ipd);
    A9_nwv         <= To_UX01(A9_ipd);
    A10_nwv        <= To_UX01(A10_ipd);
    A11_nwv        <= To_UX01(A11_ipd);
    A12_nwv        <= To_UX01(A12_ipd);
    A13_nwv        <= To_UX01(A13_ipd);
    DQ0_nwv        <= To_UX01(DQ0_ipd);
    DQ1_nwv        <= To_UX01(DQ1_ipd);
    DQ2_nwv        <= To_UX01(DQ2_ipd);
    DQ3_nwv        <= To_UX01(DQ3_ipd);
    DQ4_nwv        <= To_UX01(DQ4_ipd);
    DQ5_nwv        <= To_UX01(DQ5_ipd);
    DQ6_nwv        <= To_UX01(DQ6_ipd);
    DQ7_nwv        <= To_UX01(DQ7_ipd);
    DQS_nwv        <= To_UX01(DQS_ipd);
    DQSNeg_nwv     <= To_UX01(DQSNeg_ipd);
    TDQS_nwv        <= To_UX01(TDQS_ipd);
    TDQSNeg_nwv     <= To_UX01(TDQSNeg_ipd);
    RESETNeg_nwv   <= To_UX01(RESETNeg_ipd);
    ----------------------------------------------------------------------------
    -- Main Behavior Process
    ----------------------------------------------------------------------------

    Behavior: BLOCK

        PORT (
            ODT            : IN    std_ulogic := 'U';
            CK             : IN    std_ulogic := 'U';
            CKNeg          : IN    std_ulogic := 'U';
            CKE            : IN    std_ulogic := 'U';
            CSNeg          : IN    std_ulogic := 'U';
            RASNeg         : IN    std_ulogic := 'U';
            CASNeg         : IN    std_ulogic := 'U';
            WENeg          : IN    std_ulogic := 'U';
            RESETNeg       : IN    std_ulogic := 'U';
            BAIn           : IN    std_logic_vector(2 DOWNTO 0) :=
                                               (OTHERS => 'U');
            AIn            : IN    std_logic_vector(13 DOWNTO 0) :=
                                               (OTHERS => 'U');
            DQIn           : IN    std_logic_vector(7 DOWNTO 0) :=
                                               (OTHERS => 'U');
            DQOut          : OUT   std_ulogic_vector(7 DOWNTO 0) :=
                                               (OTHERS => 'Z');
            TDQSIn         : IN    std_ulogic := 'U';
            TDQSOut        : OUT   std_ulogic := 'Z';
            TDQSNegIn       : IN    std_ulogic := 'U';
            TDQSNegOut     : OUT   std_ulogic := 'Z';
            DQSIn          : IN    std_ulogic := 'U';
            DQSOut         : OUT   std_ulogic := 'Z';
            DQSNegIn       : IN    std_ulogic := 'U';
            DQSNegOut      : OUT   std_ulogic := 'Z'
        );

        PORT MAP (
            ODT       => ODT_nwv,
            CK        => CK_nwv,
            CKNeg     => CKNeg_nwv,
            CKE       => CKE_nwv,
            CSNeg     => CSNeg_nwv,
            RASNeg    => RASNeg_nwv,
            CASNeg    => CASNeg_nwv,
            WENeg     => WENeg_nwv,
            BAIn(0)   => BA0_nwv,
            BAIn(1)   => BA1_nwv,
            BAIn(2)   => BA2_nwv,
            AIn(0)    => A0_nwv,
            AIn(1)    => A1_nwv,
            AIn(2)    => A2_nwv,
            AIn(3)    => A3_nwv,
            AIn(4)    => A4_nwv,
            AIn(5)    => A5_nwv,
            AIn(6)    => A6_nwv,
            AIn(7)    => A7_nwv,
            AIn(8)    => A8_nwv,
            AIn(9)    => A9_nwv,
            AIn(10)   => A10_nwv,
            AIn(11)   => A11_nwv,
            AIn(12)   => A12_nwv,
            AIn(13)   => A13_nwv,
            DQIn(0)   => DQ0_nwv,
            DQIn(1)   => DQ1_nwv,
            DQIn(2)   => DQ2_nwv,
            DQIn(3)   => DQ3_nwv,
            DQIn(4)   => DQ4_nwv,