edj1308ba.vhd

vhdl cod for ram.For sp3e

--------------------------------------------------------------------------------
--  File Name: edj1308ba.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2007 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY:
--
--  version: |  author:      | mod date: | changes made:
--    V1.0     M.Novkovic      06 Nov 20   Initial release
--    V1.1     R.Miodragovic   07 June 22  Correction of state
--                                       transitions with warnings;
--                                       Implemented warnings for
--                                       time delays;
--                                       Additive latency is fixed;
--                                       Start address of write
--                                       burst is corrected;
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
--
--  Library:    RAM
--  Technology: CMOS
--  Part:       EDJ1308BA
--
--  Description: 1 Gb (16 M Words x 8 bits x 8 banks) DDR3 SDRAM
--------------------------------------------------------------------------------

LIBRARY IEEE;    USE IEEE.std_logic_1164.ALL;

                   USE IEEE.VITAL_timing.ALL;
                   USE IEEE.VITAL_primitives.ALL;

                   USE STD.textio.ALL;

LIBRARY FMF;     USE FMF.gen_utils.ALL;
                   USE FMF.conversions.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY edj1308ba IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_ODT          : VitalDelayType01 := VitalZeroDelay01;
        tipd_CK           : VitalDelayType01 := VitalZeroDelay01;
        tipd_CKNeg        : VitalDelayType01 := VitalZeroDelay01;
        tipd_CKE          : VitalDelayType01 := VitalZeroDelay01;
        tipd_CSNeg        : VitalDelayType01 := VitalZeroDelay01;
        tipd_RASNeg       : VitalDelayType01 := VitalZeroDelay01;
        tipd_CASNeg       : VitalDelayType01 := VitalZeroDelay01;
        tipd_WENeg        : VitalDelayType01 := VitalZeroDelay01;
        tipd_BA0          : VitalDelayType01 := VitalZeroDelay01;
        tipd_BA1          : VitalDelayType01 := VitalZeroDelay01;
        tipd_BA2          : VitalDelayType01 := VitalZeroDelay01;
        tipd_A0           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A1           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A2           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A3           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A4           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A5           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A6           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A7           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A8           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A9           : VitalDelayType01 := VitalZeroDelay01;
        tipd_A10          : VitalDelayType01 := VitalZeroDelay01;
        tipd_A11          : VitalDelayType01 := VitalZeroDelay01;
        tipd_A12          : VitalDelayType01 := VitalZeroDelay01;
        tipd_A13          : VitalDelayType01 := VitalZeroDelay01;

        tipd_DQ0          : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ1          : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ2          : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ3          : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ4          : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ5          : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ6          : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ7          : VitalDelayType01 := VitalZeroDelay01;

        tipd_DQS          : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQSNeg       : VitalDelayType01 := VitalZeroDelay01;
        tipd_TDQS         : VitalDelayType01 := VitalZeroDelay01;
        tipd_TDQSNeg      : VitalDelayType01 := VitalZeroDelay01;
        tipd_RESETNeg     : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_CK_DQ0        : VitalDelayType01Z := UnitDelay01Z; --  tHZ(max)
        tpd_CK_DQ1        : VitalDelayType := UnitDelay; -- tHZ(min)
        tpd_CK_DQS        : VitalDelayType01Z := UnitDelay01Z; -- tDQSCK(max)
        -- tsetup values
        tsetup_DQ0_DQS    : VitalDelayType := UnitDelay; -- tDS
        tsetup_A0_CK      : VitalDelayType := UnitDelay; -- tIS
        tsetup_DQS_CK_CL5_negedge_posedge : VitalDelayType := UnitDelay; -- tDSS
        tsetup_DQS_CK_CL6_negedge_posedge : VitalDelayType := UnitDelay; -- tDSS
        tsetup_DQS_CK_CL7_negedge_posedge : VitalDelayType := UnitDelay; -- tDSS
        tsetup_DQS_CK_CL8_negedge_posedge : VitalDelayType := UnitDelay; -- tDSS
        tsetup_DQS_CK_CL9_negedge_posedge : VitalDelayType := UnitDelay; -- tDSS
        tsetup_DQS_CK_CL10_negedge_posedge: VitalDelayType := UnitDelay; -- tDSS
        tsetup_CKE_RESETNeg               : VitalDelayType := UnitDelay;
        tsetup_CK_DQS                     : VitalDelayType := UnitDelay; -- tWLS
        -- thold values
        thold_DQ0_DQS     : VitalDelayType := UnitDelay; -- tDH
        thold_A0_CK       : VitalDelayType := UnitDelay; -- tIH
        thold_DQS_CK_CL5_posedge_posedge  : VitalDelayType := UnitDelay; -- tDSH
        thold_DQS_CK_CL6_posedge_posedge  : VitalDelayType := UnitDelay; -- tDSH
        thold_DQS_CK_CL7_posedge_posedge  : VitalDelayType := UnitDelay; -- tDSH
        thold_DQS_CK_CL8_posedge_posedge  : VitalDelayType := UnitDelay; -- tDSH
        thold_DQS_CK_CL9_posedge_posedge  : VitalDelayType := UnitDelay; -- tDSH
        thold_DQS_CK_CL10_posedge_posedge : VitalDelayType := UnitDelay; -- tDSH
        thold_CKE_RESETNeg                : VitalDelayType := UnitDelay;
        thold_CK_DQS             :  VitalDelayType := UnitDelay; -- tWLH

        -- tpw values
        tpw_CK_CL5_posedge  : VitalDelayType := UnitDelay; -- tCHAVG
        tpw_CK_CL5_negedge  : VitalDelayType := UnitDelay; -- tCLAVG
        tpw_CK_CL6_posedge  : VitalDelayType := UnitDelay; -- tCHAVG
        tpw_CK_CL6_negedge  : VitalDelayType := UnitDelay; -- tCLAVG
        tpw_CK_CL7_posedge  : VitalDelayType := UnitDelay; -- tCHAVG
        tpw_CK_CL7_negedge  : VitalDelayType := UnitDelay; -- tCLAVG
        tpw_CK_CL8_posedge  : VitalDelayType := UnitDelay; -- tCHAVG
        tpw_CK_CL8_negedge  : VitalDelayType := UnitDelay; -- tCLAVG
        tpw_CK_CL9_posedge  : VitalDelayType := UnitDelay; -- tCHAVG
        tpw_CK_CL9_negedge  : VitalDelayType := UnitDelay; -- tCLAVG
        tpw_CK_CL10_posedge : VitalDelayType := UnitDelay; -- tCHAVG
        tpw_CK_CL10_negedge : VitalDelayType := UnitDelay; -- tCLAVG
        tpw_A0_CL5          : VitalDelayType := UnitDelay; -- tIPW
        tpw_A0_CL6          : VitalDelayType := UnitDelay; -- tIPW
        tpw_A0_CL7          : VitalDelayType := UnitDelay; -- tIPW
        tpw_A0_CL8          : VitalDelayType := UnitDelay; -- tIPW
        tpw_A0_CL9          : VitalDelayType := UnitDelay; -- tIPW
        tpw_A0_CL10         : VitalDelayType := UnitDelay; -- tIPW
        tpw_DQ0_CL5         : VitalDelayType := UnitDelay; -- tDIPW
        tpw_DQ0_CL6         : VitalDelayType := UnitDelay; -- tDIPW
        tpw_DQ0_CL7         : VitalDelayType := UnitDelay; -- tDIPW
        tpw_DQ0_CL8         : VitalDelayType := UnitDelay; -- tDIPW
        tpw_DQ0_CL9         : VitalDelayType := UnitDelay; -- tDIPW
        tpw_DQ0_CL10        : VitalDelayType := UnitDelay; -- tDIPW
        tpw_DQS_normCL5_posedge  : VitalDelayType := UnitDelay; -- tDQSH
        tpw_DQS_normCL5_negedge  : VitalDelayType := UnitDelay; -- tDQSL
        tpw_DQS_normCL6_posedge  : VitalDelayType := UnitDelay; -- tDQSH
        tpw_DQS_normCL6_negedge  : VitalDelayType := UnitDelay; -- tDQSL
        tpw_DQS_normCL7_posedge  : VitalDelayType := UnitDelay; -- tDQSH
        tpw_DQS_normCL7_negedge  : VitalDelayType := UnitDelay; -- tDQSL
        tpw_DQS_normCL8_posedge  : VitalDelayType := UnitDelay; -- tDQSH
        tpw_DQS_normCL8_negedge  : VitalDelayType := UnitDelay; -- tDQSL
        tpw_DQS_normCL9_posedge  : VitalDelayType := UnitDelay; -- tDQSH
        tpw_DQS_normCL9_negedge  : VitalDelayType := UnitDelay; -- tDQSL
        tpw_DQS_normCL10_posedge : VitalDelayType := UnitDelay; -- tDQSH
        tpw_DQS_normCL10_negedge : VitalDelayType := UnitDelay; -- tDQSL
        tpw_DQS_postCL5_negedge  : VitalDelayType := UnitDelay; -- tWPST
        tpw_DQS_postCL6_negedge  : VitalDelayType := UnitDelay; -- tWPST
        tpw_DQS_postCL7_negedge  : VitalDelayType := UnitDelay; -- tWPST
        tpw_DQS_postCL8_negedge  : VitalDelayType := UnitDelay; -- tWPST
        tpw_DQS_postCL9_negedge  : VitalDelayType := UnitDelay; -- tWPST
        tpw_DQS_postCL10_negedge : VitalDelayType := UnitDelay; -- tWPST
        tpw_CKE_SelfRefresh_negedge : VitalDelayType := UnitDelay; -- tCKESR
         -- 200 us from diagram on page 58.
        tpw_RESETNeg_PoweredUp_eq_0_negedge : VitalDelayType := UnitDelay;
         -- 100 ns from diagram on page 58.
        tpw_RESETNeg_PoweredUp_eq_1_negedge : VitalDelayType := UnitDelay;

        -- tperiod values
        tperiod_CK_CL5    : VitalDelayType := UnitDelay; -- tCKAVG(min)
        tperiod_CK_CL6    : VitalDelayType := UnitDelay; -- tCKAVG(min)
        tperiod_CK_CL7    : VitalDelayType := UnitDelay; -- tCKAVG(min)
        tperiod_CK_CL8    : VitalDelayType := UnitDelay; -- tCKAVG(min)
        tperiod_CK_CL9    : VitalDelayType := UnitDelay; -- tCKAVG(min)
        tperiod_CK_CL10   : VitalDelayType := UnitDelay; -- tCKAVG(min)
        tperiod_DQS_preCL5_negedge   : VitalDelayType := UnitDelay; -- tWPRE
        tperiod_DQS_preCL6_negedge   : VitalDelayType := UnitDelay; -- tWPRE
        tperiod_DQS_preCL7_negedge   : VitalDelayType := UnitDelay; -- tWPRE
        tperiod_DQS_preCL8_negedge   : VitalDelayType := UnitDelay; -- tWPRE
        tperiod_DQS_preCL9_negedge   : VitalDelayType := UnitDelay; -- tWPRE
        tperiod_DQS_preCL10_negedge  : VitalDelayType := UnitDelay; -- tWPRE
        -- tskew values
        tskew_CK_DQS_CL5_posedge_posedge : VitalDelayType := UnitDelay; -- tDQSS
        tskew_CK_DQS_CL6_posedge_posedge : VitalDelayType := UnitDelay; -- tDQSS
        tskew_CK_DQS_CL7_posedge_posedge : VitalDelayType := UnitDelay; -- tDQSS
        tskew_CK_DQS_CL8_posedge_posedge : VitalDelayType := UnitDelay; -- tDQSS
        tskew_CK_DQS_CL9_posedge_posedge : VitalDelayType := UnitDelay; -- tDQSS
        tskew_CK_DQS_CL10_posedge_posedge: VitalDelayType := UnitDelay; -- tDQSS

        -- tdevice values: values for internal delays
        tdevice_tRC       : VitalDelayType    := 49.5 ns; -- tRC-
        tdevice_tRRD      : VitalDelayType    := 6 ns; -- tRRD-
        tdevice_tRCD      : VitalDelayType    := 13.5 ns; -- tRCD-
        tdevice_tFAW      : VitalDelayType    := 30 ns; -- tFAW-
        tdevice_tRASMIN   : VitalDelayType    := 36 ns; -- tRAS(min)-
        tdevice_tRASMAX   : VitalDelayType    := 70.2 us; -- tRAS(max)-
        tdevice_tRTP      : VitalDelayType    := 7.5 ns; -- tRTP-
        tdevice_tWR       : VitalDelayType    := 15 ns; -- tWR-
        tdevice_tWTR      : VitalDelayType    := 7.5 ns; -- tWTR-
        tdevice_tRP       : VitalDelayType    := 13.5 ns; -- tRP-
        tdevice_tRFCMIN   : VitalDelayType    := 90 ns; -- tRFC(min)-
        tdevice_tREFPer   : VitalDelayType    := 7.8 us; -- refresh period
        tdevice_tCKAVGMAX : VitalDelayType    := 3.333 ns; -- tCKAVG(max)-
        tdevice_tMRD      : VitalDelayType    := 6 ns; -- tMRD -
        tdevice_tMOD      : VitalDelayType    := 22.5 ns; -- tMRD -
        tdevice_tXPR      : VitalDelayType    := 7.5 ns; -- tXPR -
        tdevice_tZQINIT   : VitalDelayType    := 384 ns; -- tZQINIT
        tdevice_tZQOPER   : VitalDelayType    := 768 ns; -- tZQOPER
        tdevice_tZQCS     : VitalDelayType    := 96 ns; -- tZQCS
        tdevice_tCKSRX    : VitalDelayType    := 7.5 ns; -- tCKSRX
        tdevice_tCKSRE    : VitalDelayType    := 7.5 ns; -- tCKSRE
        tdevice_tCKESR    : VitalDelayType    := 7.5 ns; -- tCKESR
        tdevice_tWLDQSEN  : VitalDelayType    := 37.5 ns; -- tWLDQSEN
        tdevice_tWLMRD    : VitalDelayType    := 60 ns; -- tWLMRD
        tdevice_tWLOMAX   : VitalDelayType    := 10 ns; -- tWLO(MAX)
        tdevice_tWLOEMAX  : VitalDelayType    := 2 ns; -- tWLOE(MAX)

        -- generic control parameters
        InstancePath      : string    := DefaultInstancePath;
        TimingChecksOn    : boolean   := DefaultTimingChecks;
        MsgOn             : boolean   := DefaultMsgOn;
        XOn               : boolean   := DefaultXon;

        -- memory file to be loaded
        mem_file_name     : string    := "none";
        UserPreload       : boolean   := FALSE;

        -- For FMF SDF technology file usage
        TimingModel       : string    := DefaultTimingModel
    );
    PORT (
        ODT             : IN    std_ulogic := 'U';
        CK              : IN    std_ulogic := 'U';
        CKNeg           : IN    std_ulogic := 'U';
        CKE             : IN    std_ulogic := 'U';
        CSNeg           : IN    std_ulogic := 'U';
        RASNeg          : IN    std_ulogic := 'U';
        CASNeg          : IN    std_ulogic := 'U';
        WENeg           : IN    std_ulogic := 'U';
        BA0             : IN    std_ulogic := 'U';
        BA1             : IN    std_ulogic := 'U';
        BA2             : IN    std_ulogic := 'U';
        A0              : IN    std_ulogic := 'U';
        A1              : IN    std_ulogic := 'U';
        A2              : IN    std_ulogic := 'U';
        A3              : IN    std_ulogic := 'U';
        A4              : IN    std_ulogic := 'U';
        A5              : IN    std_ulogic := 'U';
        A6              : IN    std_ulogic := 'U';
        A7              : IN    std_ulogic := 'U';
        A8              : IN    std_ulogic := 'U';
        A9              : IN    std_ulogic := 'U';
        A10             : IN    std_ulogic := 'U';
        A11             : IN    std_ulogic := 'U';
        A12             : IN    std_ulogic := 'U';
        A13             : IN    std_ulogic := 'U';
        DQ0             : INOUT std_ulogic := 'U';
        DQ1             : INOUT std_ulogic := 'U';
        DQ2             : INOUT std_ulogic := 'U';