idt70t3319dd.vhd

vhdl cod for ram.For sp3e

                CheckEnabled    =>  PLNegL='1' );

            VitalPeriodPulseCheck (
                TestSignal      =>  ClockL,
                TestSignalName  =>  "Left Clock",
                Period          =>  tperiod_CLKR,
                PulseWidthLow   =>  tpw_CLKR_negedge,
                PulseWidthHigh  =>  tpw_CLKR_posedge,
                PeriodData      =>  PD_CLKF,
                XOn             =>  XOn,
                MsgOn           =>  MsgOn,
                Violation       =>  Pviol_CLKF,
                HeaderMsg       =>  InstancePath & PartID,
                CheckEnabled    =>  PLNegL='0' );

            VitalPeriodPulseCheck (
                TestSignal      =>  ClockR,
                TestSignalName  =>  "Right Clock",
                Period          =>  tperiod_CLKL,
                PulseWidthLow   =>  tpw_CLKL_negedge,
                PulseWidthHigh  =>  tpw_CLKL_posedge,
                PeriodData      =>  PD_CLKP1,
                XOn             =>  XOn,
                MsgOn           =>  MsgOn,
                Violation       =>  Pviol_CLKP1,
                HeaderMsg       =>  InstancePath & PartID,
                CheckEnabled    =>  PLNegL='1' );

            VitalPeriodPulseCheck (
                TestSignal      =>  ClockL,
                TestSignalName  =>  "Left Clock",
                Period          =>  tperiod_CLKR,
                PulseWidthLow   =>  tpw_CLKR_negedge,
                PulseWidthHigh  =>  tpw_CLKR_posedge,
                PeriodData      =>  PD_CLKF1,
                XOn             =>  XOn,
                MsgOn           =>  MsgOn,
                Violation       =>  Pviol_CLKF1,
                HeaderMsg       =>  InstancePath & PartID,
                CheckEnabled    =>  PLNegL='0' );

             Violation := Tviol_AL_CLK OR Tviol_AR_CLK OR Tviol_DL_CLK OR
                          Tviol_DR_CLK OR Tviol_CEL_CLK OR Tviol_CER_CLK OR
                          Tviol_UBEL_CLK OR Tviol_UBER_CLK OR Tviol_RWL_CLK OR
                          Tviol_RWR_CLK OR Tviol_ADSL_CLK OR Tviol_ADSR_CLK
                          OR Tviol_CNTL_CLK OR Tviol_CNTR_CLK OR
                          Tviol_RPTL_CLK OR Tviol_RPTR_CLK OR
                          Pviol_CLKP OR Pviol_CLKF OR Pviol_CLKP1 OR
                          Pviol_CLKF1 OR Tviol_LBEL_CLK OR Tviol_LBER_CLK;

            Viol <= Violation;

            ASSERT Violation = '0'
                REPORT InstancePath & partID & ": simulation may be" &
                " inaccurate due to timing violations"
                SEVERITY WARNING;

        END IF;

    END PROCESS TimingCheckP;

    ---------------------------------------------------------------------------
    -- register input data for left port
    ---------------------------------------------------------------------------
    BothPort : PROCESS (AddressL, DataInL, RWL, CEL, OEL, ClockL, PLNegL,
                          ADSNegL, CNTENNegL, REPEATNegL, BENegL, ZZL,
                          AddressR, DataInR, RWR, CER, OER, ClockR, PLNegR,
                          ADSNegR, CNTENNegR, REPEATNegR, UBNegR, LBNegR, ZZR)

        FILE mem_file           : text  is  mem_file_name;
        VARIABLE ind            : NATURAL RANGE 0 TO MemSize := 0;
        VARIABLE buf            : line;


        VARIABLE L_cntS, L_cntR     : NATURAL RANGE 0 TO 4 := 0;
        VARIABLE R_cntS, R_cntR     : NATURAL RANGE 0 TO 4 := 0;

        VARIABLE L_BE_reg1, L_BE_reg2 : std_logic_vector(1 downto 0) := "00";
        VARIABLE L_BE_out, L_BE_mux   : std_logic_vector(1 downto 0) := "00";
        VARIABLE L_CE_reg1, L_CE_reg2 : std_logic := '0';
        VARIABLE L_CE_mux           : std_logic := '0';
        VARIABLE L_DOut_reg, L_D_mux: std_logic_vector(17 downto 0);
        VARIABLE L_RW_reg           : std_logic := '0';
        VARIABLE Addr_reg_L         : NATURAL RANGE 0 TO MemSize := 0;

        VARIABLE R_BE_reg1, R_BE_reg2 : std_logic_vector(1 downto 0) := "00";
        VARIABLE R_BE_out, R_BE_mux   : std_logic_vector(1 downto 0) := "00";
        VARIABLE R_CE_reg1, R_CE_reg2 : std_logic := '0';
        VARIABLE R_CE_mux             : std_logic := '0';
        VARIABLE R_DOut_reg, R_D_mux  : std_logic_vector(17 downto 0);
        VARIABLE R_RW_reg             : std_logic := '0';
        VARIABLE Addr_reg_R           : NATURAL RANGE 0 TO MemSize := 0;

        VARIABLE CollisionL     : boolean := FALSE;
        VARIABLE CollisionR     : boolean := FALSE;

        TYPE mem_state IS ( desel,      -- port not selected
                            read,       -- read from port
                            write,      -- write to port
                            collision); -- memory collision

        VARIABLE L_state      : mem_state;
        VARIABLE Addr_L       : NATURAL RANGE 0 TO MemSize := 0;

        VARIABLE R_state      : mem_state;
        VARIABLE Addr_R       : NATURAL RANGE 0 TO MemSize := 0;
            --registers
        VARIABLE ColL_pipe1     : std_logic := '1';
        VARIABLE ColL_pipe2     : std_logic := '1';
        VARIABLE ColL_zd        : std_logic;
        VARIABLE ColR_pipe1     : std_logic := '1';
        VARIABLE ColR_pipe2     : std_logic := '1';
        VARIABLE ColR_zd        : std_logic;

        VARIABLE Linterrupt     : std_logic := '1';
        VARIABLE Rinterrupt     : std_logic := '1';

        VARIABLE ColL_GlitchData : VitalGlitchDataType;
        VARIABLE ColR_GlitchData : VitalGlitchDataType;
        VARIABLE IntL_GlitchData : VitalGlitchDataType;
        VARIABLE IntR_GlitchData : VitalGlitchDataType;
        -- Memory array declaration
        TYPE mem_type IS ARRAY(0 to MemSize) OF INTEGER RANGE -2 TO MaxData;

        VARIABLE MemDatA     : mem_type := (OTHERS => -2); --(17 :  9)
        VARIABLE MemDatB     : mem_type := (OTHERS => -2); --(8  :  0)

        VARIABLE int_ZZL      : std_logic := '0';
        VARIABLE int_ZZR      : std_logic := '0';

        VARIABLE DataOutL_zd : std_logic_vector(17 downto 0);
        VARIABLE DataOutR_zd : std_logic_vector(17 downto 0);
        VARIABLE DL_out      : std_logic_vector(17 downto 0);
        VARIABLE DL_in       : std_logic_vector(17 downto 0);
        VARIABLE BEL_in      : std_logic_vector(1 downto 0);

        VARIABLE CEL_reg     : std_logic;
        VARIABLE RWL_reg     : std_logic;

        VARIABLE DR_out      : std_logic_vector(17 downto 0);
        VARIABLE DR_in       : std_logic_vector(17 downto 0);
        VARIABLE BER_in      : std_logic_vector(1 downto 0);

        VARIABLE CER_reg     : std_logic;
        VARIABLE RWR_reg     : std_logic;

    BEGIN
    --left sleep ctrl
        IF rising_edge(ClockL) THEN
            IF ZZL='1' THEN
                IF L_cntS < 3 THEN
                    L_cntS := L_cntS +1;
                    L_cntR := 0;
                ELSE
                    int_ZZL := '1';
                END IF;
            ELSE
                IF L_cntR < 4 THEN
                    L_cntR := L_cntR +1;
                    L_cntS := 0;
                ELSE
                    int_ZZL := '0';
                END IF;
            END IF;
        END IF;
    --right sleep ctrl
        IF rising_edge(ClockR) THEN
            IF ZZR='1' THEN
                IF R_cntS < 3 THEN
                    R_cntS := R_cntS +1;
                    R_cntR := 0;
                ELSE
                    int_ZZR := '1';
                END IF;
            ELSE
                IF R_cntR < 4 THEN
                    R_cntR := R_cntR +1;
                    R_cntS := 0;
                ELSE
                    int_ZZR := '0';
                END IF;
            END IF;
        END IF;

    --left PL/F selection
        IF rising_edge(ClockL) THEN
            L_RW_reg := RWL;
            L_CE_reg2 := L_CE_reg1;
            L_CE_reg1 := CEL(1) AND (NOT CEL(0));
            L_DOut_reg := DL_Out;
            L_BE_reg2 := L_BE_reg1;
            L_BE_reg1 := BENegL;

            -- control signals for memory
            BEL_in(0) := (NOT L_BE_reg1(0)) AND L_CE_reg1 AND (NOT L_RW_reg);
            BEL_in(1) := (NOT L_BE_reg1(1)) AND L_CE_reg1 AND (NOT L_RW_reg);
            RWL_reg := L_RW_reg;
            CEL_reg := L_CE_reg1; --

            IF PLNegL='1' THEN
                L_BE_mux := L_BE_reg2;
                L_CE_mux := L_CE_reg2;
            ELSE
                L_BE_mux := L_BE_reg1;
                L_CE_mux := L_CE_reg1;
            END IF;
        END IF;

    --right PL/F selection
        IF rising_edge(ClockR) THEN
            R_RW_reg := RWR;
            R_CE_reg2 := R_CE_reg1;
            R_CE_reg1 := CER(1) AND (NOT CER(0));
            R_BE_reg2 := R_BE_reg1;
            R_BE_reg1 := BENegR;

            -- control signals for memory
            BER_in(0) := (NOT R_BE_reg1(0)) AND R_CE_reg1 AND (NOT R_RW_reg);
            BER_in(1) := (NOT R_BE_reg1(1)) AND R_CE_reg1 AND (NOT R_RW_reg);
            RWR_reg := R_RW_reg;
            CER_reg := R_CE_reg1; --

            IF PLNegR='1' THEN
                R_BE_mux := R_BE_reg2;
                R_CE_mux := R_CE_reg2;
            ELSE
                R_BE_mux := R_BE_reg1;
                R_CE_mux := R_CE_reg1;
            END IF;
        END IF;

    -- left address counter
        IF rising_edge(ClockL) AND int_ZZL /= '1'  THEN
            IF REPEATNegL='0' THEN  -- set counter to last valid ADS load
                Addr_L := Addr_reg_L;
            ELSIF ADSNegL='0' AND REPEATNegL='1' THEN --load address
                Addr_L := to_nat(AddressL);
                Addr_reg_L := to_nat(AddressL);
            ELSIF ADSNegL='1' AND REPEATNegL='1' AND CNTEnNegL='0' THEN --count
                Addr_L := Addr_L + 1;
            END IF;
            IF RWL_reg='1' THEN -- read
                L_state := read;
            ELSE
                L_state := write;
            END IF;
        ELSE
            L_state := desel;
        END IF;

    -- right address counter
        IF rising_edge(ClockR) AND int_ZZR /= '1'  THEN
            IF REPEATNegR='0' THEN  -- set counter to last valid ADS load
                Addr_R := Addr_reg_R;
            ELSIF ADSNegR='0' AND REPEATNegR='1' THEN --load address
                Addr_R := to_nat(AddressR);
                Addr_reg_R := to_nat(AddressR);
            ELSIF ADSNegR='1' AND REPEATNegR='1' AND CNTEnNegR='0' THEN --count
                Addr_R := Addr_R + 1;
            END IF;
            IF RWR_reg='1' THEN -- read
                R_state := read;
            ELSE
                R_state := write;
            END IF;
        ELSE
            R_state := desel;
        END IF;

        IF rising_edge(ClockL) AND CEL_reg = '1' AND int_ZZL /= '1'  THEN
            IF Addr_L = Addr_R THEN
                IF (L_state=read OR L_state=write) AND
                   (R_state=write OR right='1') THEN
                    CollisionL := TRUE;
                ELSE
                    CollisionL := FALSE;
                END IF;
            E