idt70t3319dd.vhd

vhdl cod for ram.For sp3e

        COLNegL           : OUT   std_logic;

        AddressR          : IN    std_logic_vector(HiAddrBit downto 0);
        DataInR           : IN    std_logic_vector(17 downto 0);
        DataOutR          : OUT   std_logic_vector(17 downto 0);
        RWR               : IN    std_logic;
        CER               : IN    std_logic_vector(1 downto 0);
        OER               : IN    std_logic;
        ClockR            : IN    std_logic;
        PLNegR            : IN    std_logic;
        ADSNegR           : IN    std_logic;
        CNTENNegR         : IN    std_logic;
        REPEATNegR        : IN    std_logic;
        BENegR            : IN    std_logic_vector(1 downto 0);
        ZZR               : IN    std_logic;
        INTNegR           : OUT   std_logic;
        COLNegR           : OUT   std_logic
    );
    PORT MAP (
        AddressL(0 )    => A0L_ipd   ,
        AddressL(1 )    => A1L_ipd   ,
        AddressL(2 )    => A2L_ipd   ,
        AddressL(3 )    => A3L_ipd   ,
        AddressL(4 )    => A4L_ipd   ,
        AddressL(5 )    => A5L_ipd   ,
        AddressL(6 )    => A6L_ipd   ,
        AddressL(7 )    => A7L_ipd   ,
        AddressL(8 )    => A8L_ipd   ,
        AddressL(9 )    => A9L_ipd   ,
        AddressL(10)    => A10L_ipd ,
        AddressL(11)    => A11L_ipd ,
        AddressL(12)    => A12L_ipd ,
        AddressL(13)    => A13L_ipd ,
        AddressL(14)    => A14L_ipd ,
        AddressL(15)    => A15L_ipd ,
        AddressL(16)    => A16L_ipd ,
        AddressL(17)    => A17L_ipd ,

        DataInL(0 )     => IO0L_ipd    ,
        DataInL(1 )     => IO1L_ipd    ,
        DataInL(2 )     => IO2L_ipd    ,
        DataInL(3 )     => IO3L_ipd    ,
        DataInL(4 )     => IO4L_ipd    ,
        DataInL(5 )     => IO5L_ipd    ,
        DataInL(6 )     => IO6L_ipd    ,
        DataInL(7 )     => IO7L_ipd    ,
        DataInL(8 )     => IO8L_ipd    ,
        DataInL(9 )     => IO9L_ipd    ,
        DataInL(10)     => IO10L_ipd   ,
        DataInL(11)     => IO11L_ipd   ,
        DataInL(12)     => IO12L_ipd   ,
        DataInL(13)     => IO13L_ipd   ,
        DataInL(14)     => IO14L_ipd   ,
        DataInL(15)     => IO15L_ipd   ,
        DataInL(16)     => IO16L_ipd   ,
        DataInL(17)     => IO17L_ipd   ,

        DataOutL(0 )    => IO0L    ,
        DataOutL(1 )    => IO1L    ,
        DataOutL(2 )    => IO2L    ,
        DataOutL(3 )    => IO3L    ,
        DataOutL(4 )    => IO4L    ,
        DataOutL(5 )    => IO5L    ,
        DataOutL(6 )    => IO6L    ,
        DataOutL(7 )    => IO7L    ,
        DataOutL(8 )    => IO8L    ,
        DataOutL(9 )    => IO9L    ,
        DataOutL(10)    => IO10L   ,
        DataOutL(11)    => IO11L   ,
        DataOutL(12)    => IO12L   ,
        DataOutL(13)    => IO13L   ,
        DataOutL(14)    => IO14L   ,
        DataOutL(15)    => IO15L   ,
        DataOutL(16)    => IO16L   ,
        DataOutL(17)    => IO17L   ,

        RWL             => RWL_ipd       ,
        CEL(0)          => CE0NegL_ipd   ,
        CEL(1)          => CE1L_ipd      ,
        OEL             => OENegL_ipd   ,
        ClockL          => CLKL_ipd      ,
        CNTENNegL       => CNTENNegL_ipd ,
        PLNegL          => PLNegL_ipd    ,
        ADSNegL         => ADSNegL_ipd   ,
        REPEATNegL      => REPEATNegL_ipd,
        BENegL(1)       => UBNegL_ipd   ,
        BENegL(0)       => LBNegL_ipd   ,
        ZZL             => ZZL_ipd       ,
        INTNegL         => INTNegL       ,
        COLNegL         => COLNegL       ,

        AddressR(0 )    => A0R_ipd   ,
        AddressR(1 )    => A1R_ipd   ,
        AddressR(2 )    => A2R_ipd   ,
        AddressR(3 )    => A3R_ipd   ,
        AddressR(4 )    => A4R_ipd   ,
        AddressR(5 )    => A5R_ipd   ,
        AddressR(6 )    => A6R_ipd   ,
        AddressR(7 )    => A7R_ipd   ,
        AddressR(8 )    => A8R_ipd   ,
        AddressR(9 )    => A9R_ipd   ,
        AddressR(10)    => A10R_ipd ,
        AddressR(11)    => A11R_ipd ,
        AddressR(12)    => A12R_ipd ,
        AddressR(13)    => A13R_ipd ,
        AddressR(14)    => A14R_ipd ,
        AddressR(15)    => A15R_ipd ,
        AddressR(16)    => A16R_ipd ,
        AddressR(17)    => A17R_ipd ,

        DataInR(0 )     => IO0R_ipd    ,
        DataInR(1 )     => IO1R_ipd    ,
        DataInR(2 )     => IO2R_ipd    ,
        DataInR(3 )     => IO3R_ipd    ,
        DataInR(4 )     => IO4R_ipd    ,
        DataInR(5 )     => IO5R_ipd    ,
        DataInR(6 )     => IO6R_ipd    ,
        DataInR(7 )     => IO7R_ipd    ,
        DataInR(8 )     => IO8R_ipd    ,
        DataInR(9 )     => IO9R_ipd    ,
        DataInR(10)     => IO10R_ipd   ,
        DataInR(11)     => IO11R_ipd   ,
        DataInR(12)     => IO12R_ipd   ,
        DataInR(13)     => IO13R_ipd   ,
        DataInR(14)     => IO14R_ipd   ,
        DataInR(15)     => IO15R_ipd   ,
        DataInR(16)     => IO16R_ipd   ,
        DataInR(17)     => IO17R_ipd   ,

        DataOutR(0 )    => IO0R    ,
        DataOutR(1 )    => IO1R    ,
        DataOutR(2 )    => IO2R    ,
        DataOutR(3 )    => IO3R    ,
        DataOutR(4 )    => IO4R    ,
        DataOutR(5 )    => IO5R    ,
        DataOutR(6 )    => IO6R    ,
        DataOutR(7 )    => IO7R    ,
        DataOutR(8 )    => IO8R    ,
        DataOutR(9 )    => IO9R    ,
        DataOutR(10)    => IO10R   ,
        DataOutR(11)    => IO11R   ,
        DataOutR(12)    => IO12R   ,
        DataOutR(13)    => IO13R   ,
        DataOutR(14)    => IO14R   ,
        DataOutR(15)    => IO15R   ,
        DataOutR(16)    => IO16R   ,
        DataOutR(17)    => IO17R   ,

        RWR             => RWR_ipd       ,
        CER(0)          => CE0NegR_ipd   ,
        CER(1)          => CE1R_ipd      ,
        OER             => OENegR_ipd   ,
        ClockR          => CLKR_ipd      ,
        CNTENNegR       => CNTENNegR_ipd ,
        PLNegR          => PLNegR_ipd    ,
        ADSNegR         => ADSNegR_ipd   ,
        REPEATNegR      => REPEATNegR_ipd,
        BENegR(1)       => UBNegR_ipd   ,
        BENegR(0)       => LBNegR_ipd   ,
        ZZR             => ZZR_ipd       ,
        INTNegR         => INTNegR       ,
        COLNegR         => COLNegR
    );

    SIGNAL DOL_zd  : std_logic_vector(17 downto 0);
    SIGNAL DOR_zd  : std_logic_vector(17 downto 0);
    SIGNAL Viol    : X01 := '0';

BEGIN
-------------------------------------------------------------------------------
-- Timing Check
-------------------------------------------------------------------------------
    TimingCheckP: PROCESS(AddressL, DataInL, RWL, CEL, OEL, ClockL, PLNegL,
                          ADSNegL, CNTENNegL, REPEATNegL, BENegL,
                          AddressR, DataInR, RWR, CER, OER, ClockR, PLNegR,
                          ADSNegR, CNTENNegR, REPEATNegR, UBNegR, LBNegR)
        -- VARIABLE
        VARIABLE Violation        : X01 := '0';

        VARIABLE TD_AL_CLK          : VitalTimingDataType;
        VARIABLE Tviol_AL_CLK       : X01 := '0';
        VARIABLE TD_AR_CLK          : VitalTimingDataType;
        VARIABLE Tviol_AR_CLK       : X01 := '0';
        VARIABLE TD_DL_CLK          : VitalTimingDataType;
        VARIABLE Tviol_DL_CLK       : X01 := '0';
        VARIABLE TD_DR_CLK          : VitalTimingDataType;
        VARIABLE Tviol_DR_CLK       : X01 := '0';
        VARIABLE TD_CEL_CLK         : VitalTimingDataType;
        VARIABLE Tviol_CEL_CLK      : X01 := '0';
        VARIABLE TD_CER_CLK         : VitalTimingDataType;
        VARIABLE Tviol_CER_CLK      : X01 := '0';
        VARIABLE TD_UBEL_CLK        : VitalTimingDataType;
        VARIABLE Tviol_UBEL_CLK     : X01 := '0';
        VARIABLE TD_LBEL_CLK        : VitalTimingDataType;
        VARIABLE Tviol_LBEL_CLK     : X01 := '0';
        VARIABLE TD_UBER_CLK        : VitalTimingDataType;
        VARIABLE Tviol_UBER_CLK     : X01 := '0';
        VARIABLE TD_LBER_CLK        : VitalTimingDataType;
        VARIABLE Tviol_LBER_CLK     : X01 := '0';
        VARIABLE TD_RWL_CLK         : VitalTimingDataType;
        VARIABLE Tviol_RWL_CLK      : X01 := '0';
        VARIABLE TD_RWR_CLK         : VitalTimingDataType;
        VARIABLE Tviol_RWR_CLK      : X01 := '0';
        VARIABLE TD_ADSL_CLK        : VitalTimingDataType;
        VARIABLE Tviol_ADSL_CLK     : X01 := '0';
        VARIABLE TD_ADSR_CLK        : VitalTimingDataType;
        VARIABLE Tviol_ADSR_CLK     : X01 := '0';
        VARIABLE TD_CNTL_CLK        : VitalTimingDataType;
        VARIABLE Tviol_CNTL_CLK     : X01 := '0';
        VARIABLE TD_CNTR_CLK        : VitalTimingDataType;
        VARIABLE Tviol_CNTR_CLK     : X01 := '0';
        VARIABLE TD_RPTL_CLK        : VitalTimingDataType;
        VARIABLE Tviol_RPTL_CLK     : X01 := '0';
        VARIABLE TD_RPTR_CLK        : VitalTimingDataType;
        VARIABLE Tviol_RPTR_CLK     : X01 := '0';
        VARIABLE TD_TDI_TCK         : VitalTimingDataType;
        VARIABLE Tviol_TDI_TCK      : X01 := '0';
        VARIABLE PD_CLKP            : VitalPeriodDataType :=
                                                   VitalPeriodDataInit;
        VARIABLE Pviol_CLKP         : X01 := '0';
        VARIABLE PD_CLKF            : VitalPeriodDataType :=
                                                   VitalPeriodDataInit;
        VARIABLE Pviol_CLKF         : X01 := '0';
        VARIABLE PD_CLKP1           : VitalPeriodDataType :=
                                                   VitalPeriodDataInit;
        VARIABLE Pviol_CLKP1        : X01 := '0';
        VARIABLE PD_CLKF1           : VitalPeriodDataType :=
                                                   VitalPeriodDataInit;
        VARIABLE Pviol_CLKF1        : X01 := '0';
        VARIABLE PD_TCK             : VitalPeriodDataType :=
                                                   VitalPeriodDataInit;
        VARIABLE Pviol_TCK          : X01 := '0';
        VARIABLE PD_TRST            : VitalPeriodDataType :=
                                                   VitalPeriodDataInit;
        VARIABLE Pviol_TRST         : X01 := '0';

    BEGIN
        IF TimingChecksOn THEN

            VitalSetupHoldCheck (
                TestSignal      => AddressL,
                TestSignalName  => "Left Address",
                RefSignal       => ClockL,
                RefSignalName   => "ClockL",
                SetupHigh       => tsetup_A0L_CLKL,
                SetupLow        => tsetup_A0L_CLKL,
                HoldHigh        => thold_A0L_CLKL,
                HoldLow         => thold_A0L_CLKL,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_AL_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_AL_CLK );

            VitalSetupHoldCheck (
                TestSignal      => AddressR,
                TestSignalName  => "Right Address",
                RefSignal       => ClockR,
                RefSignalName   => "ClockR",
                SetupHigh       => tsetup_A0L_CLKL,
                SetupLow        => tsetup_A0L_CLKL,
                HoldHigh        => thold_A0L_CLKL,
                HoldLow         => thold_A0L_CLKL,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_AR_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_AR_CLK );

            VitalSetupHoldCheck (
                TestSignal      => DataInL,
                TestSignalName  => "Left Data",
                RefSignal       => ClockL,
                RefSignalName   => "ClockL",