idt70t3319dd.vhd

vhdl cod for ram.For sp3e

        IO12R            : INOUT    std_logic := 'U';
        IO13R            : INOUT    std_logic := 'U';
        IO14R            : INOUT    std_logic := 'U';
        IO15R            : INOUT    std_logic := 'U';
        IO16R            : INOUT    std_logic := 'U';
        IO17R            : INOUT    std_logic := 'U';
        --Right port controml lines
        CE0NegR          : IN    std_logic := 'U';
        CE1R             : IN    std_logic := 'U';
        OENegR           : IN    std_logic := 'U';
        RWR              : IN    std_logic := 'U';
        CLKR             : IN    std_logic := 'U';
        PLNegR           : IN    std_logic := 'U';
        ADSNegR          : IN    std_logic := 'U';
        CNTENNegR        : IN    std_logic := 'U';
        REPEATNegR       : IN    std_logic := 'U';
        UBNegR           : IN    std_logic := 'U';
        LBNegR           : IN    std_logic := 'U';
        ZZR              : IN    std_logic := 'U';
        --Right port outputs
        INTNegR          : OUT   std_logic := 'U';   --INterrupt
        COLNegR          : OUT   std_logic := 'U'    --Collision Alert
    );
    ATTRIBUTE VITAL_LEVEL0 of idt70t3319dd : ENTITY IS TRUE;
END idt70t3319dd;

-------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
-------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of idt70t3319dd IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT partID         : STRING  := "idt70t3319dd";
    CONSTANT HiAddrBit      : NATURAL := 17;
    CONSTANT MaxData        : NATURAL := 511;
    CONSTANT MemSize        : NATURAL := (2**(HiAddrBit+1))-1;--0x3FFFF=256K
    CONSTANT MailBoxL       : NATURAL := MemSize-1;
    CONSTANT MailBoxR       : NATURAL := MemSize;

    SIGNAL A0L_ipd          : std_ulogic := 'U';
    SIGNAL A1L_ipd          : std_ulogic := 'U';
    SIGNAL A2L_ipd          : std_ulogic := 'U';
    SIGNAL A3L_ipd          : std_ulogic := 'U';
    SIGNAL A4L_ipd          : std_ulogic := 'U';
    SIGNAL A5L_ipd          : std_ulogic := 'U';
    SIGNAL A6L_ipd          : std_ulogic := 'U';
    SIGNAL A7L_ipd          : std_ulogic := 'U';
    SIGNAL A8L_ipd          : std_ulogic := 'U';
    SIGNAL A9L_ipd          : std_ulogic := 'U';
    SIGNAL A10L_ipd         : std_ulogic := 'U';
    SIGNAL A11L_ipd         : std_ulogic := 'U';
    SIGNAL A12L_ipd         : std_ulogic := 'U';
    SIGNAL A13L_ipd         : std_ulogic := 'U';
    SIGNAL A14L_ipd         : std_ulogic := 'U';
    SIGNAL A15L_ipd         : std_ulogic := 'U';
    SIGNAL A16L_ipd         : std_ulogic := 'U';
    SIGNAL A17L_ipd         : std_ulogic := 'U';
    --Left port IO lines
    SIGNAL IO0L_ipd         : std_ulogic := 'U';
    SIGNAL IO1L_ipd         : std_ulogic := 'U';
    SIGNAL IO2L_ipd         : std_ulogic := 'U';
    SIGNAL IO3L_ipd         : std_ulogic := 'U';
    SIGNAL IO4L_ipd         : std_ulogic := 'U';
    SIGNAL IO5L_ipd         : std_ulogic := 'U';
    SIGNAL IO6L_ipd         : std_ulogic := 'U';
    SIGNAL IO7L_ipd         : std_ulogic := 'U';
    SIGNAL IO8L_ipd         : std_ulogic := 'U';
    SIGNAL IO9L_ipd         : std_ulogic := 'U';
    SIGNAL IO10L_ipd        : std_ulogic := 'U';
    SIGNAL IO11L_ipd        : std_ulogic := 'U';
    SIGNAL IO12L_ipd        : std_ulogic := 'U';
    SIGNAL IO13L_ipd        : std_ulogic := 'U';
    SIGNAL IO14L_ipd        : std_ulogic := 'U';
    SIGNAL IO15L_ipd        : std_ulogic := 'U';
    SIGNAL IO16L_ipd        : std_ulogic := 'U';
    SIGNAL IO17L_ipd        : std_ulogic := 'U';
    --Left port control
    SIGNAL CE0NegL_ipd      : std_ulogic := 'U';
    SIGNAL CE1L_ipd         : std_ulogic := 'U';
    SIGNAL OENegL_ipd       : std_ulogic := 'U';
    SIGNAL RWL_ipd          : std_ulogic := 'U';
    SIGNAL CLKL_ipd         : std_ulogic := 'U';
    SIGNAL PLNegL_ipd       : std_ulogic := 'U';
    SIGNAL ADSNegL_ipd      : std_ulogic := 'U';
    SIGNAL CNTENNegL_ipd    : std_ulogic := 'U';
    SIGNAL REPEATNegL_ipd   : std_ulogic := 'U';
    SIGNAL UBNegL_ipd       : std_ulogic := 'U';
    SIGNAL LBNegL_ipd       : std_ulogic := 'U';
    SIGNAL ZZL_ipd          : std_ulogic := 'U';

    --Right port Address lines
    SIGNAL A0R_ipd          : std_ulogic := 'U';
    SIGNAL A1R_ipd          : std_ulogic := 'U';
    SIGNAL A2R_ipd          : std_ulogic := 'U';
    SIGNAL A3R_ipd          : std_ulogic := 'U';
    SIGNAL A4R_ipd          : std_ulogic := 'U';
    SIGNAL A5R_ipd          : std_ulogic := 'U';
    SIGNAL A6R_ipd          : std_ulogic := 'U';
    SIGNAL A7R_ipd          : std_ulogic := 'U';
    SIGNAL A8R_ipd          : std_ulogic := 'U';
    SIGNAL A9R_ipd          : std_ulogic := 'U';
    SIGNAL A10R_ipd         : std_ulogic := 'U';
    SIGNAL A11R_ipd         : std_ulogic := 'U';
    SIGNAL A12R_ipd         : std_ulogic := 'U';
    SIGNAL A13R_ipd         : std_ulogic := 'U';
    SIGNAL A14R_ipd         : std_ulogic := 'U';
    SIGNAL A15R_ipd         : std_ulogic := 'U';
    SIGNAL A16R_ipd         : std_ulogic := 'U';
    SIGNAL A17R_ipd         : std_ulogic := 'U';
    --Right port IO lines
    SIGNAL IO0R_ipd         : std_ulogic := 'U';
    SIGNAL IO1R_ipd         : std_ulogic := 'U';
    SIGNAL IO2R_ipd         : std_ulogic := 'U';
    SIGNAL IO3R_ipd         : std_ulogic := 'U';
    SIGNAL IO4R_ipd         : std_ulogic := 'U';
    SIGNAL IO5R_ipd         : std_ulogic := 'U';
    SIGNAL IO6R_ipd         : std_ulogic := 'U';
    SIGNAL IO7R_ipd         : std_ulogic := 'U';
    SIGNAL IO8R_ipd         : std_ulogic := 'U';
    SIGNAL IO9R_ipd         : std_ulogic := 'U';
    SIGNAL IO10R_ipd        : std_ulogic := 'U';
    SIGNAL IO11R_ipd        : std_ulogic := 'U';
    SIGNAL IO12R_ipd        : std_ulogic := 'U';
    SIGNAL IO13R_ipd        : std_ulogic := 'U';
    SIGNAL IO14R_ipd        : std_ulogic := 'U';
    SIGNAL IO15R_ipd        : std_ulogic := 'U';
    SIGNAL IO16R_ipd        : std_ulogic := 'U';
    SIGNAL IO17R_ipd        : std_ulogic := 'U';
     --Right port controml lines
    SIGNAL CE0NegR_ipd      : std_ulogic := 'U';
    SIGNAL CE1R_ipd         : std_ulogic := 'U';
    SIGNAL OENegR_ipd       : std_ulogic := 'U';
    SIGNAL RWR_ipd          : std_ulogic := 'U';
    SIGNAL CLKR_ipd         : std_ulogic := 'U';
    SIGNAL PLNegR_ipd       : std_ulogic := 'U';
    SIGNAL ADSNegR_ipd      : std_ulogic := 'U';
    SIGNAL CNTENNegR_ipd    : std_ulogic := 'U';
    SIGNAL REPEATNegR_ipd   : std_ulogic := 'U';
    SIGNAL UBNegR_ipd       : std_ulogic := 'U';
    SIGNAL LBNegR_ipd       : std_ulogic := 'U';
    SIGNAL ZZR_ipd          : std_ulogic := 'U';

    SIGNAL left_in          : std_ulogic := '0';
    SIGNAL left             : std_ulogic := '0';
    SIGNAL right_in         : std_ulogic := '0';
    SIGNAL right            : std_ulogic := '0';

BEGIN
    ---------------------------------------------------------------------------
    -- Internal Delays
    ---------------------------------------------------------------------------
    -- Artificial VITAL primitives to incorporate internal delays
    TCCS : VitalBuf (left , left_in , (VitalZeroDelay,tdevice_TCO)); --left
    TCCS1: VitalBuf (right, right_in, (VitalZeroDelay,tdevice_TCO)); --right

    ---------------------------------------------------------------------------
    -- Wire Delays
    ---------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN
        w_1   : VitalWireDelay (OENegL_ipd    , OENegL    , tipd_OENegL );
        w_2   : VitalWireDelay (A0L_ipd       , A0L       , tipd_A0L  );
        w_3   : VitalWireDelay (A1L_ipd       , A1L       , tipd_A1L  );
        w_4   : VitalWireDelay (A2L_ipd       , A2L       , tipd_A2L  );
        w_5   : VitalWireDelay (A3L_ipd       , A3L       , tipd_A3L  );
        w_6   : VitalWireDelay (A4L_ipd       , A4L       , tipd_A4L  );
        w_7   : VitalWireDelay (A5L_ipd       , A5L       , tipd_A5L  );
        w_8   : VitalWireDelay (A6L_ipd       , A6L       , tipd_A6L  );
        w_9   : VitalWireDelay (A7L_ipd       , A7L       , tipd_A7L  );
        w_10  : VitalWireDelay (A8L_ipd       , A8L       , tipd_A8L  );
        w_11  : VitalWireDelay (A9L_ipd       , A9L       , tipd_A9L  );
        w_12  : VitalWireDelay (A10L_ipd      , A10L      , tipd_A10L );
        w_13  : VitalWireDelay (A11L_ipd      , A11L      , tipd_A11L );
        w_14  : VitalWireDelay (A12L_ipd      , A12L      , tipd_A12L );
        w_15  : VitalWireDelay (A13L_ipd      , A13L      , tipd_A13L );
        w_16  : VitalWireDelay (A14L_ipd      , A14L      , tipd_A14L );
        w_17  : VitalWireDelay (A15L_ipd      , A15L      , tipd_A15L );
        w_18  : VitalWireDelay (A16L_ipd      , A16L      , tipd_A16L );
        w_19  : VitalWireDelay (A17L_ipd      , A17L      , tipd_A17L );
        w_20  : VitalWireDelay (IO0L_ipd      , IO0L      , tipd_IO0L );
        w_21  : VitalWireDelay (IO1L_ipd      , IO1L      , tipd_IO1L );
        w_22  : VitalWireDelay (IO2L_ipd      , IO2L      , tipd_IO2L );
        w_23  : VitalWireDelay (IO3L_ipd      , IO3L      , tipd_IO3L );
        w_24  : VitalWireDelay (IO4L_ipd      , IO4L      , tipd_IO4L );
        w_25  : VitalWireDelay (IO5L_ipd      , IO5L      , tipd_IO5L );
        w_26  : VitalWireDelay (IO6L_ipd      , IO6L      , tipd_IO6L );
        w_27  : VitalWireDelay (IO7L_ipd      , IO7L      , tipd_IO7L );
        w_28  : VitalWireDelay (IO8L_ipd      , IO8L      , tipd_IO8L );
        w_29  : VitalWireDelay (IO9L_ipd      , IO9L      , tipd_IO9L );
        w_30  : VitalWireDelay (IO10L_ipd     , IO10L     , tipd_IO10L);
        w_31  : VitalWireDelay (IO11L_ipd     , IO11L     , tipd_IO11L);
        w_32  : VitalWireDelay (IO12L_ipd     , IO12L     , tipd_IO12L);
        w_33  : VitalWireDelay (IO13L_ipd     , IO13L     , tipd_IO13L);
        w_34  : VitalWireDelay (IO14L_ipd     , IO14L     , tipd_IO14L);
        w_35  : VitalWireDelay (IO15L_ipd     , IO15L     , tipd_IO15L);
        w_36  : VitalWireDelay (IO16L_ipd     , IO16L     , tipd_IO16L);
        w_37  : VitalWireDelay (IO17L_ipd     , IO17L     , tipd_IO17L);
        w_56  : VitalWireDelay (CE0NegL_ipd   , CE0NegL   , tipd_CE0NegL   );
        w_57  : VitalWireDelay (CE1L_ipd      , CE1L      , tipd_CE1L      );
        w_58  : VitalWireDelay (RWL_ipd       , RWL       , tipd_RWL       );
        w_59  : VitalWireDelay (CLKL_ipd      , CLKL      , tipd_CLKL      );
        w_60  : VitalWireDelay (ADSNegL_ipd   , ADSNegL   , tipd_ADSNegL   );
        w_61  : VitalWireDelay (CNTENNegL_ipd , CNTENNegL , tipd_CNTENNegL );
        w_62  : VitalWireDelay (REPEATNegL_ipd, REPEATNegL, tipd_REPEATNegL);
        w_65  : VitalWireDelay (UBNegL_ipd   , UBNegL   , tipd_UBNegL   );
        w_66  : VitalWireDelay (LBNegL_ipd   , LBNegL   , tipd_LBNegL   );
        w_67  : VitalWireDelay (ZZL_ipd       , ZZL       , tipd_ZZL       );
        w_68  : VitalWireDelay (A0R_ipd       , A0R       , tipd_A0R       );
        w_69  : VitalWireDelay (A1R_ipd       , A1R       , tipd_A1R       );
        w_70  : VitalWireDelay (A2R_ipd       , A2R       , tipd_A2R       );
        w_71  : VitalWireDelay (A3R_ipd       , A3R       , tipd_A3R       );
        w_72  : VitalWireDelay (A4R_ipd       , A4R       , tipd_A4R       );
        w_73  : VitalWireDelay (A5R_ipd       , A5R       , tipd_A5R       );
        w_74  : VitalWireDelay (A6R_ipd       , A6R       , tipd_A6R );
        w_75  : VitalWireDelay (A7R_ipd       , A7R       , tipd_A7R );
        w_76  : VitalWireDelay (A8R_ipd       , A8R       , tipd_A8R );
        w_77  : VitalWireDelay (A9R_ipd       , A9R       , tipd_A9R );
        w_78  : VitalWireDelay (A10R_ipd      , A10R      , tipd_A10R);
        w_79  : VitalWireDelay (A11R_ipd      , A11R      , tipd_A11R);
        w_80  : VitalWireDelay (A12R_ipd      , A12R      , tipd_A12R);
        w_81  : VitalWireDelay (A13R_ipd      , A13R      , tipd_A13R);
        w_82  : VitalWireDelay (A14R_ipd      , A14R      , tipd_A14R);
        w_83  : VitalWireDelay (A15R_ipd      , A15R      , tipd_A15R);
        w_84  : VitalWireDelay (A16R_ipd      , A16R      , tipd_A16R);
        w_85  : VitalWireDelay (A17R_ipd      , A17R      , tipd_A17R);
        w_86  : VitalWireDelay (IO0R_ipd      , IO0R      , tipd_IO0R);
        w_87  : VitalWireDelay (IO1R_ipd      , IO1R      , tipd_IO1R);
        w_88  : VitalWireDelay (IO2R_ipd      , IO2R      , tipd_IO2R);
        w_89  : VitalWireDelay (IO3R_ipd      , IO3R      , tipd_IO3R);
        w_90  : VitalWireDelay (IO4R_ipd      , IO4R      , tipd_IO4R);
        w_91  : VitalWireDelay (IO5R_ipd      , IO5R      , tipd_IO5R);
        w_92  : VitalWireDelay (IO6R_ipd      , IO6R      , tipd_IO6R );
        w_93  : VitalWireDelay (IO7R_ipd      , IO7R      , tipd_IO7R );
        w_94  : VitalWireDelay (IO8R_ipd      , IO8R      , tipd_IO8R );
        w_95  : VitalWireDelay (IO9R_ipd      , IO9R      , tipd_IO9R );
        w_96  : VitalWireDelay (IO10R_ipd     , IO10R     , tipd_IO10R);
        w_97  : VitalWireDelay (IO11R_ipd     , IO11R     , tipd_IO11R);
        w_98  : VitalWireDelay (IO12R_ipd     , IO12R     , tipd_IO12R);
        w_99  : VitalWireDelay (IO13R_ipd     , IO13R     , tipd_IO13R);
        w_100 : VitalWireDelay (IO14R_ipd     , IO14R     , tipd_IO14R);
        w_101 : VitalWireDelay (IO15R_ipd     , IO15R     , tipd_IO15R);
        w_102 : VitalWireDelay (IO16R_ipd     , IO16R     , tipd_IO16R);
        w_103 : VitalWireDelay (IO17R_ipd     , IO17R     , tipd_IO17R);
        w_123 : VitalWireDelay (CE0NegR_ipd   , CE0NegR   , tipd_CE0NegR);
        w_124 : VitalWireDelay (CE1R_ipd      , CE1R      , tipd_CE1R );
        w_125 : VitalWireDelay (RWR_ipd       , RWR       , tipd_RWR   );
        w_126 : VitalWireDelay (CLKR_ipd      , CLKR      , tipd_CLKR );
        w_127 : VitalWireDelay (ADSNegR_ipd   , ADSNegR   , tipd_ADSNegR);
        w_128 : VitalWireDelay (CNTENNegR_ipd , CNTENNegR , tipd_CNTENNegR);
        w_129 : VitalWireDelay (REPEATNegR_ipd, REPEATNegR, tipd_REPEATNegR);
        w_132 : VitalWireDelay (UBNegR_ipd   , UBNegR   , tipd_UBNegR);
        w_133 : VitalWireDelay (LBNegR_ipd   , LBNegR   , tipd_LBNegR);
        w_134 : VitalWireDelay (ZZR_ipd       , ZZR       , tipd_ZZR    );
        w_139 : VitalWireDelay (OENegR_ipd    , OENegR    , tipd_OENegR );
        w_140 : VitalWireDelay (PLNegL_ipd    , PLNegL    , tipd_PLNegL );
        w_141 : VitalWireDelay (PLNegR_ipd    , PLNegR    , tipd_PLNegR );

    END BLOCK;

    ---------------------------------------------------------------------------
    -- Main Behavior Block
    ---------------------------------------------------------------------------
    Behavior: BLOCK
    PORT (
        AddressL          : IN    std_logic_vector(HiAddrBit downto 0);
        DataInL           : IN    std_logic_vector(17 downto 0);
        DataOutL          : OUT   std_logic_vector(17 downto 0);
        RWL               : IN    std_logic;
        CEL               : IN    std_logic_vector(1 downto 0);
        OEL               : IN    std_logic;
        ClockL            : IN    std_logic;
        PLNegL            : IN    std_logic;
        ADSNegL           : IN    std_logic;
        CNTENNegL         : IN    std_logic;
        REPEATNegL        : IN    std_logic;
        BENegL            : IN    std_logic_vector(1 downto 0);
        ZZL               : IN    std_logic;
        INTNegL           : OUT   std_logic;