idt70t3319dd.ftm
来自「vhdl cod for ram.For sp3e」· FTM 代码 · 共 62 行
FTM
62 行
<!DOCTYPE FTML SYSTEM "ftml.dtd"><FTML><HEAD><TITLE>FMF Timing for idt70t3319dd Parts</TITLE><BODY><REVISION.HISTORY>version: | author: | mod date: | changes made: V1.0 R. Munden 03 Oct 18 Initial release V1.1 R. Munden 08 Jun 08 Correct port names</REVISION.HISTORY><TIMESCALE>1ns</TIMESCALE><MODEL>idt70t3319dd<FMFTIME>IDT70T3319S166DD<SOURCE>Integrated Device Technology DSC 5652/5 February 2006</SOURCE><COMMENT>The Values listed are for VCC=2.5V +/- 100mV, CL=10pF, Ta=0 to 70C</COMMENT><COMMENT>For each parameter where only minimum or maximum values were provided by the vendor, other values are derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLKL ColNegL (1.2:2.4:3.6) (1.2:2.4:3.6)) (IOPATH CLKL IntNegL (2.3:4.6:7) (2.3:4.6:7)) (IOPATH CLKL IO0L (1.2:2.4:3.6) (1.2:2.4:3.6) (1:2.4:3.6) (1:2.4:3.6) (1:2.4:3.6) (1:2.4:3.6)) (IOPATH CLKR IO0R (4:8:12) (4:8:12) (1:2.4:3.6) (1:8:12) (1:2.4:3.6) (1:8:12)) (IOPATH OENegL IO0L () () (1:2.4:3.6) (1:2.9:4.4) (1:2.4:3.6) (1:2.9:4.4)) )) (TIMINGCHECK (SETUP A0L CLKL (1.7)) (HOLD A0L CLKL (0.5)) (WIDTH (posedge CLKL) (2.4)) (WIDTH (negedge CLKL) (2.4)) (WIDTH (posedge CLKR) (8)) (WIDTH (negedge CLKR) (8)) (PERIOD CLKR (20)) (PERIOD CLKL (6)) )) (CELL (CELLTYPE "VITALbuf") (INSTANCE %LABEL%/TCO) (DELAY (ABSOLUTE (DEVICE(5))))</TIMING></FMFTIME><FMFTIME>IDT70T3319S133DD<SOURCE>Integrated Device Technology DSC 5652/5 February 2006</SOURCE><COMMENT>The Values listed are for VCC=2.5V +/- 100mV, CL=10pF, Ta=0 to 70C</COMMENT><COMMENT>For each parameter where only minimum or maximum values were provided by the vendor, other values are derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLKL ColNegL (1.4:2.8:4.2) (1.4:2.8:4.2)) (IOPATH CLKL IntNegL (2.3:4.6:7) (2.3:4.6:7)) (IOPATH CLKL IO0L (1.4:2.8:4.2) (1.4:2.8:4.2) (1:2.8:4.2) (1:2.8:4.2) (1:2.8:4.2) (1:2.8:4.2)) (IOPATH CLKR IO0R (5:10:15) (5:10:15) (1:2.8:4.2) (1:10:15) (1:2.8:4.2) (1:10:15)) (IOPATH OENegL IO0L () () (1:2.8:4.2) (1:3.1:4.6) (1:2.8:4.2) (1:3.1:4.6)) )) (TIMINGCHECK (SETUP A0L CLKL (1.8)) (HOLD A0L CLKL (0.5)) (WIDTH (posedge CLKL) (3)) (WIDTH (negedge CLKL) (3)) (WIDTH (posedge CLKR) (10)) (WIDTH (negedge CLKR) (10)) (PERIOD CLKR (25)) (PERIOD CLKL (7.5)) )) (CELL (CELLTYPE "VITALbuf") (INSTANCE %LABEL%/TCO) (DELAY (ABSOLUTE (DEVICE(6))))</TIMING></FMFTIME></BODY></FTML>⌨️ 快捷键说明
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