idt70v5388.vhd

vhdl cod for ram.For sp3e

    -- Main Behavior Block
    ----------------------------------------------------------------------------
    Behavior: BLOCK

        PORT (
            AddressP1In       : IN    std_logic_vector(15 downto 0);
            AddressP1Out      : OUT   std_logic_vector(15 downto 0);
            AddressP2In       : IN    std_logic_vector(15 downto 0);
            AddressP2Out      : OUT   std_logic_vector(15 downto 0);
            AddressP3In       : IN    std_logic_vector(15 downto 0);
            AddressP3Out      : OUT   std_logic_vector(15 downto 0);
            AddressP4In       : IN    std_logic_vector(15 downto 0);
            AddressP4Out      : OUT   std_logic_vector(15 downto 0);
            DatA1In           : IN    std_logic_vector(8 downto 0);
            DatB1In           : IN    std_logic_vector(8 downto 0);
            DataP1Out         : OUT   std_logic_vector(17 downto 0)
                                                     := (others => 'Z');
            DatA2In           : IN    std_logic_vector(8 downto 0);
            DatB2In           : IN    std_logic_vector(8 downto 0);
            DataP2Out         : OUT   std_logic_vector(17 downto 0)
                                                     := (others => 'Z');
            DatA3In           : IN    std_logic_vector(8 downto 0);
            DatB3In           : IN    std_logic_vector(8 downto 0);
            DataP3Out         : OUT   std_logic_vector(17 downto 0)
                                                     := (others => 'Z');
            DatA4In           : IN    std_logic_vector(8 downto 0);
            DatB4In           : IN    std_logic_vector(8 downto 0);
            DataP4Out         : OUT   std_logic_vector(17 downto 0)
                                                     := (others => 'Z');
            CLKIn             : IN    std_logic_vector(3 downto 0);
            MRSTNegIn         : IN    std_ulogic := 'U';
            RWIn              : IN    std_logic_vector(3 downto 0);
            OENegIn           : IN    std_logic_vector(3 downto 0);
            CE0NegIn          : IN    std_logic_vector(3 downto 0);
            CE1In             : IN    std_logic_vector(3 downto 0);
            UBNegIn           : IN    std_logic_vector(3 downto 0);
            LBNegIn           : IN    std_logic_vector(3 downto 0);
            CNTLDNegIn        : IN    std_logic_vector(3 downto 0);
            CNTINCNegIn       : IN    std_logic_vector(3 downto 0);
            CNTRDNegIn        : IN    std_logic_vector(3 downto 0);
            CNTRSTNegIn       : IN    std_logic_vector(3 downto 0);
            CNTINTNegOut      : OUT   std_logic_vector(3 downto 0)
                                                     := (others => 'Z');
            MKLDNegIn         : IN    std_logic_vector(3 downto 0);
            MKRDNegIn         : IN    std_logic_vector(3 downto 0);
            INTNegOut         : OUT   std_logic_vector(3 downto 0)
                                                     := (others => 'Z');
            TMSIn             : IN    std_ulogic := 'U';
            TRSTNegIn         : IN    std_ulogic := 'U';
            TCKIn             : IN    std_ulogic := 'U';
            TDIIn             : IN    std_ulogic := 'U';
            TDOOut            : OUT   std_ulogic := 'U';
            CLKMBISTIn        : IN    std_ulogic := 'U'
        );
        PORT MAP (
            AddressP1In(0) => A0P1_ipd,
            AddressP1In(1) => A1P1_ipd,
            AddressP1In(2) => A2P1_ipd,
            AddressP1In(3) => A3P1_ipd,
            AddressP1In(4) => A4P1_ipd,
            AddressP1In(5) => A5P1_ipd,
            AddressP1In(6) => A6P1_ipd,
            AddressP1In(7) => A7P1_ipd,
            AddressP1In(8) => A8P1_ipd,
            AddressP1In(9) => A9P1_ipd,
            AddressP1In(10) => A10P1_ipd,
            AddressP1In(11) => A11P1_ipd,
            AddressP1In(12) => A12P1_ipd,
            AddressP1In(13) => A13P1_ipd,
            AddressP1In(14) => A14P1_ipd,
            AddressP1In(15) => A15P1_ipd,
            AddressP2In(0) => A0P2_ipd,
            AddressP2In(1) => A1P2_ipd,
            AddressP2In(2) => A2P2_ipd,
            AddressP2In(3) => A3P2_ipd,
            AddressP2In(4) => A4P2_ipd,
            AddressP2In(5) => A5P2_ipd,
            AddressP2In(6) => A6P2_ipd,
            AddressP2In(7) => A7P2_ipd,
            AddressP2In(8) => A8P2_ipd,
            AddressP2In(9) => A9P2_ipd,
            AddressP2In(10) => A10P2_ipd,
            AddressP2In(11) => A11P2_ipd,
            AddressP2In(12) => A12P2_ipd,
            AddressP2In(13) => A13P2_ipd,
            AddressP2In(14) => A14P2_ipd,
            AddressP2In(15) => A15P2_ipd,
            AddressP3In(0) => A0P3_ipd,
            AddressP3In(1) => A1P3_ipd,
            AddressP3In(2) => A2P3_ipd,
            AddressP3In(3) => A3P3_ipd,
            AddressP3In(4) => A4P3_ipd,
            AddressP3In(5) => A5P3_ipd,
            AddressP3In(6) => A6P3_ipd,
            AddressP3In(7) => A7P3_ipd,
            AddressP3In(8) => A8P3_ipd,
            AddressP3In(9) => A9P3_ipd,
            AddressP3In(10) => A10P3_ipd,
            AddressP3In(11) => A11P3_ipd,
            AddressP3In(12) => A12P3_ipd,
            AddressP3In(13) => A13P3_ipd,
            AddressP3In(14) => A14P3_ipd,
            AddressP3In(15) => A15P3_ipd,
            AddressP4In(0) => A0P4_ipd,
            AddressP4In(1) => A1P4_ipd,
            AddressP4In(2) => A2P4_ipd,
            AddressP4In(3) => A3P4_ipd,
            AddressP4In(4) => A4P4_ipd,
            AddressP4In(5) => A5P4_ipd,
            AddressP4In(6) => A6P4_ipd,
            AddressP4In(7) => A7P4_ipd,
            AddressP4In(8) => A8P4_ipd,
            AddressP4In(9) => A9P4_ipd,
            AddressP4In(10) => A10P4_ipd,
            AddressP4In(11) => A11P4_ipd,
            AddressP4In(12) => A12P4_ipd,
            AddressP4In(13) => A13P4_ipd,
            AddressP4In(14) => A14P4_ipd,
            AddressP4In(15) => A15P4_ipd,
            AddressP1Out(0) => A0P1,
            AddressP1Out(1) => A1P1,
            AddressP1Out(2) => A2P1,
            AddressP1Out(3) => A3P1,
            AddressP1Out(4) => A4P1,
            AddressP1Out(5) => A5P1,
            AddressP1Out(6) => A6P1,
            AddressP1Out(7) => A7P1,
            AddressP1Out(8) => A8P1,
            AddressP1Out(9) => A9P1,
            AddressP1Out(10) => A10P1,
            AddressP1Out(11) => A11P1,
            AddressP1Out(12) => A12P1,
            AddressP1Out(13) => A13P1,
            AddressP1Out(14) => A14P1,
            AddressP1Out(15) => A15P1,
            AddressP2Out(0) => A0P2,
            AddressP2Out(1) => A1P2,
            AddressP2Out(2) => A2P2,
            AddressP2Out(3) => A3P2,
            AddressP2Out(4) => A4P2,
            AddressP2Out(5) => A5P2,
            AddressP2Out(6) => A6P2,
            AddressP2Out(7) => A7P2,
            AddressP2Out(8) => A8P2,
            AddressP2Out(9) => A9P2,
            AddressP2Out(10) => A10P2,
            AddressP2Out(11) => A11P2,
            AddressP2Out(12) => A12P2,
            AddressP2Out(13) => A13P2,
            AddressP2Out(14) => A14P2,
            AddressP2Out(15) => A15P2,
            AddressP3Out(0) => A0P3,
            AddressP3Out(1) => A1P3,
            AddressP3Out(2) => A2P3,
            AddressP3Out(3) => A3P3,
            AddressP3Out(4) => A4P3,
            AddressP3Out(5) => A5P3,
            AddressP3Out(6) => A6P3,
            AddressP3Out(7) => A7P3,
            AddressP3Out(8) => A8P3,
            AddressP3Out(9) => A9P3,
            AddressP3Out(10) => A10P3,
            AddressP3Out(11) => A11P3,
            AddressP3Out(12) => A12P3,
            AddressP3Out(13) => A13P3,
            AddressP3Out(14) => A14P3,
            AddressP3Out(15) => A15P3,
            AddressP4Out(0) => A0P4,
            AddressP4Out(1) => A1P4,
            AddressP4Out(2) => A2P4,
            AddressP4Out(3) => A3P4,
            AddressP4Out(4) => A4P4,
            AddressP4Out(5) => A5P4,
            AddressP4Out(6) => A6P4,
            AddressP4Out(7) => A7P4,
            AddressP4Out(8) => A8P4,
            AddressP4Out(9) => A9P4,
            AddressP4Out(10) => A10P4,
            AddressP4Out(11) => A11P4,
            AddressP4Out(12) => A12P4,
            AddressP4Out(13) => A13P4,
            AddressP4Out(14) => A14P4,
            AddressP4Out(15) => A15P4,
            DatA1In(0) => IO0P1_ipd,
            DatA1In(1) => IO1P1_ipd,
            DatA1In(2) => IO2P1_ipd,
            DatA1In(3) => IO3P1_ipd,
            DatA1In(4) => IO4P1_ipd,
            DatA1In(5) => IO5P1_ipd,
            DatA1In(6) => IO6P1_ipd,
            DatA1In(7) => IO7P1_ipd,
            DatA1In(8) => IO8P1_ipd,
            DatB1In(0) => IO9P1_ipd,
            DatB1In(1) => IO10P1_ipd,
            DatB1In(2) => IO11P1_ipd,
            DatB1In(3) => IO12P1_ipd,
            DatB1In(4) => IO13P1_ipd,
            DatB1In(5) => IO14P1_ipd,
            DatB1In(6) => IO15P1_ipd,
            DatB1In(7) => IO16P1_ipd,
            DatB1In(8) => IO17P1_ipd,
            DatA2In(0) => IO0P2_ipd,
            DatA2In(1) => IO1P2_ipd,
            DatA2In(2) => IO2P2_ipd,
            DatA2In(3) => IO3P2_ipd,
            DatA2In(4) => IO4P2_ipd,
            DatA2In(5) => IO5P2_ipd,
            DatA2In(6) => IO6P2_ipd,
            DatA2In(7) => IO7P2_ipd,
            DatA2In(8) => IO8P2_ipd,
            DatB2In(0) => IO9P2_ipd,
            DatB2In(1) => IO10P2_ipd,
            DatB2In(2) => IO11P2_ipd,
            DatB2In(3) => IO12P2_ipd,
            DatB2In(4) => IO13P2_ipd,
            DatB2In(5) => IO14P2_ipd,
            DatB2In(6) => IO15P2_ipd,
            DatB2In(7) => IO16P2_ipd,
            DatB2In(8) => IO17P2_ipd,
            DatA3In(0) => IO0P3_ipd,
            DatA3In(1) => IO1P3_ipd,
            DatA3In(2) => IO2P3_ipd,
            DatA3In(3) => IO3P3_ipd,
            DatA3In(4) => IO4P3_ipd,
            DatA3In(5) => IO5P3_ipd,
            DatA3In(6) => IO6P3_ipd,
            DatA3In(7) => IO7P3_ipd,