cy7c185.vhd

vhdl cod for ram.For sp3e

            DataIn(7) =>  D7_ipd,
            AddressIn(0) => A0_ipd,
            AddressIn(1) => A1_ipd,
            AddressIn(2) => A2_ipd,
            AddressIn(3) => A3_ipd,
            AddressIn(4) => A4_ipd,
            AddressIn(5) => A5_ipd,
            AddressIn(6) => A6_ipd,
            AddressIn(7) => A7_ipd,
            AddressIn(8) => A8_ipd,
            AddressIn(9) => A9_ipd,
            AddressIn(10) => A10_ipd,
            AddressIn(11) => A11_ipd,
            AddressIn(12) => A12_ipd,
            OENegIn => OENeg_ipd,
            WENegIn => WENeg_ipd,
            CE1NegIn => CE1Neg_ipd,
            CE2In => CE2_ipd
        );

        SIGNAL weneg_int : std_ulogic;

    BEGIN 

        weneg_int <= (WENegIn OR CE1NegIn) OR not CE2In;

        ------------------------------------------------------------------------
        -- Behavior Process
        ------------------------------------------------------------------------
        Behavior : PROCESS (OENegIn, WENegIn, CE1NegIn, CE2In, AddressIn,
                            DataIn, weneg_int)
                         
            CONSTANT OENeg_D_Delay : VitalDelayArrayType01ZX
                      (HiDbit downto 0) := (OTHERS => tpd_OENeg_D0);

            CONSTANT CE1Neg_D_Delay :VitalDelayArrayType01ZX
                      (HiDbit downto 0) := (OTHERS => tpd_CE1Neg_D0);

            CONSTANT CE2_D_Delay :VitalDelayArrayType01ZX
                      (HiDbit downto 0) := (OTHERS => tpd_CE2_D0);

            CONSTANT Addr_D_Delay : VitalDelayArrayType01ZX
                      (DlyArraySize downto 0) := (OTHERS => tpd_A0_D0);

            -- Timing Check Variables
            VARIABLE Tviol_A0_WENeg: X01 := '0';
            VARIABLE TD_A0_WENeg   : VitalTimingDataType;

            VARIABLE Tviol_D0_WENeg: X01 := '0';
            VARIABLE TD_D0_WENeg   : VitalTimingDataType;

            VARIABLE Tviol_D0_CENeg: X01 := '0';
            VARIABLE TD_D0_CENeg   : VitalTimingDataType;

            VARIABLE Pviol_WENeg   : X01 := '0';
            VARIABLE PD_WENeg      : VitalPeriodDataType := VitalPeriodDataInit;

            -- VITAL Memory Declaration
            VARIABLE Memdat : VitalMemoryDataType :=
                VitalDeclareMemory (
                    NoOfWords            => TotalLOC,
                    NoOfBitsPerWord      => DataWidth,
                    NoOfBitsPerSubWord   => DataWidth,
                    MemoryLoadFile       => MemLoadFileName,
                    BinaryLoadFile       => FALSE
                );

            -- Functionality Results Variables
            VARIABLE Violation  : X01 := '0';
            VARIABLE D_zd     : std_logic_vector(HiDbit DOWNTO 0);

            VARIABLE Prevcntls    : std_logic_vector(0 to 3);
            VARIABLE PrevData     : std_logic_vector(HiDbit downto 0);
            VARIABLE Prevaddr     : std_logic_vector(HiAbit downto 0);
            VARIABLE PFlag        : VitalPortFlagVectorType(0 downto 0);
            VARIABLE Addrvalue    : VitalAddressValueType;
            VARIABLE OENegChange  : TIME := 0 ns;
            VARIABLE CE1NegChange : TIME := 0 ns;
            VARIABLE CE2Change    : TIME := 0 ns;
            VARIABLE AddrChangeArray  : VitalTimeArrayT(HiAbit downto 0);

            VARIABLE D_GlitchData : VitalGlitchDataArrayType(HiDbit Downto 0);
            VARIABLE DSchedData   : VitalMemoryScheduleDataVectorType
                                    (HiDbit Downto 0);

        BEGIN 

            --------------------------------------------------------------------
            -- Timing Check Section
            --------------------------------------------------------------------
            IF (TimingChecksOn) THEN

                VitalSetupHoldCheck (
                    TestSignal      => AddressIn,
                    TestSignalName  => "Address",
                    RefSignal       => weneg_int,
                    RefSignalName   => "WENeg",
                    SetupHigh       => tsetup_A0_WENeg,
                    SetupLow        => tsetup_A0_WENeg,
                    CheckEnabled    => (CE1NegIn ='0' AND CE2In = '1'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_A0_WENeg,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_A0_WENeg );

                VitalSetupHoldCheck (
                    TestSignal      => DataIn,
                    TestSignalName  => "Data",
                    RefSignal       => weneg_int,
                    RefSignalName   => "Write End",
                    SetupHigh       => tsetup_D0_WENeg,
                    SetupLow        => tsetup_D0_WENeg,
                    HoldHigh        => thold_D0_WENeg,
                    HoldLow         => thold_D0_WENeg,
                    CheckEnabled    => (CE1NegIn ='0' AND CE2In = '1'
                                        AND OENeg ='1'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_D0_WENeg,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_D0_WENeg );

                VitalPeriodPulseCheck (
                    TestSignal      =>  WENegIn,
                    TestSignalName  =>  "WENeg",
                    PulseWidthLow   =>  tpw_WENeg_negedge,
                    PeriodData      =>  PD_WENeg,
                    XOn             =>  XOn,
                    MsgOn           =>  MsgOn,
                    Violation       =>  Pviol_WENeg,
                    HeaderMsg       =>  InstancePath & PartID,
                    CheckEnabled    =>  TRUE );

                Violation := Pviol_WENeg OR Tviol_D0_WENeg OR Tviol_D0_CENeg;

                ASSERT Violation = '0'
                    REPORT InstancePath & partID & ": simulation may be" &
                           " inaccurate due to timing violations"
                    SEVERITY SeverityMode;

            END IF; -- Timing Check Section

            --------------------------------------------------------------------
            -- Functional Section
            --------------------------------------------------------------------
            VitalMemoryTable (
                DataOutBus     => D_zd,
                MemoryData     => Memdat,
                PrevControls   => Prevcntls,
                PrevDataInBus  => Prevdata,
                PrevAddressBus => Prevaddr,
                PortFlag       => PFlag,
                Controls       => (CE2In, CE1NegIn, OENegIn, WENegIn),
                DataInBus      => DataIn,
                AddressBus     => AddressIn,
                AddressValue   => Addrvalue,
                MemoryTable    => Table_generic_sram
            );

            --------------------------------------------------------------------
            -- Output Section
            --------------------------------------------------------------------
            VitalMemoryInitPathDelay (
                ScheduleDataArray   => DSchedData,
                OutputDataArray     => D_zd
            );

            VitalMemoryAddPathDelay (
                ScheduleDataArray     => DSchedData,
                InputSignal           => OENegIn,
                OutputSignalName      => "D",
                InputChangeTime       => OENegChange,
                PathDelayArray        => OENeg_D_Delay,
                ArcType               => CrossArc,
                PathCondition         => true,
                OutputRetainFlag      => true
            );

            VitalMemoryAddPathDelay (
                ScheduleDataArray     => DSchedData,
                InputSignal           => CE1NegIn,
                OutputSignalName      => "D",
                InputChangeTime       => CE1NegChange,
                PathDelayArray        => CE1Neg_D_Delay,
                ArcType               => CrossArc,
                PathCondition         => true,
                OutputRetainFlag      => false
            );

            VitalMemoryAddPathDelay (
                ScheduleDataArray     => DSchedData,
                InputSignal           => CE2In,
                OutputSignalName      => "D",
                InputChangeTime       => CE2Change,
                PathDelayArray        => CE2_D_Delay,
                ArcType               => CrossArc,
                PathCondition         => true,
                OutputRetainFlag      => false
            );

            VitalMemoryAddPathDelay (
                ScheduleDataArray     => DSchedData,
                InputSignal           => AddressIn,
                OutputSignalName      => "D",
                InputChangeTimeArray  => AddrChangeArray,
                PathDelayArray        => Addr_D_Delay,
                ArcType               => CrossArc,
                OutputRetainFlag      => true,
                OutputRetainBehavior  => BitCorrupt,
                PathCondition         => OENegIn = '0'
            );

            VitalMemorySchedulePathDelay (
                OutSignal            => DataOut,
                OutputSignalName     => "D",
                ScheduleDataArray   => DSchedData
            );

        END PROCESS;                           

    END BLOCK;
END vhdl_behavioral;