idt70914.vhd

vhdl cod for ram.For sp3e

            --------------------------------------------------------------------
            -- Timing Check Section
            --------------------------------------------------------------------
            IF (TimingChecksOn) THEN

                VitalSetupHoldCheck (
                    TestSignal      => ALIn,
                    TestSignalName  => "AL",
                    RefSignal       => CLKLIn,
                    RefSignalName   => "CLKL",
                    SetupHigh       => tsetup_AR0_CLKR,
                    SetupLow        => tsetup_AR0_CLKR,
                    HoldHigh        => thold_AR0_CLKR,
                    CheckEnabled    => TRUE,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_ALIn_CLKLIn,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_ALIn_CLKLIn );

                VitalSetupHoldCheck (
                    TestSignal      => ARIn,
                    TestSignalName  => "AR",
                    RefSignal       => CLKRIn,
                    RefSignalName   => "CLKR",
                    SetupHigh       => tsetup_AR0_CLKR,
                    SetupLow        => tsetup_AR0_CLKR,
                    HoldHigh        => thold_AR0_CLKR,
                    HoldLow         => thold_AR0_CLKR,
                    CheckEnabled    => TRUE,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_ARIn_CLKRIn,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_ARIn_CLKRIn );

                VitalSetupHoldCheck (
                    TestSignal      => CLKENLNegIn,
                    TestSignalName  => "CLKENLNeg",
                    RefSignal       => CLKLIn,
                    RefSignalName   => "CLKL",
                    SetupHigh       => tsetup_CLKENRNeg_CLKR,
                    SetupLow        => tsetup_CLKENRNeg_CLKR,
                    HoldHigh        => thold_CLKENRNeg_CLKR,
                    HoldLow         => thold_CLKENRNeg_CLKR,
                    CheckEnabled    => TRUE,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_CLKENLNegIn_CLKLIn,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_CLKENLNegIn_CLKLIn );

                VitalSetupHoldCheck (
                    TestSignal      => CLKENRNegIn,
                    TestSignalName  => "CLKENRNeg",
                    RefSignal       => CLKRIn,
                    RefSignalName   => "CLKR",
                    SetupHigh       => tsetup_CLKENRNeg_CLKR,
                    SetupLow        => tsetup_CLKENRNeg_CLKR,
                    HoldHigh        => thold_CLKENRNeg_CLKR,
                    HoldLow         => thold_CLKENRNeg_CLKR,
                    CheckEnabled    => TRUE,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_CLKENRNegIn_CLKRIn,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_CLKENRNegIn_CLKRIn );

               VitalPeriodPulseCheck (
                    TestSignal      =>  CLKLIn,
                    TestSignalName  =>  "CLKL",
                    Period          =>  tperiod_CLKR,
                    PulseWidthLow   =>  tpw_CLKR,
                    PulseWidthHigh  =>  tpw_CLKR,
                    PeriodData      =>  TD_CLKLIn,
                    XOn             =>  XOn,
                    MsgOn           =>  MsgOn,
                    HeaderMsg       =>  InstancePath & PartID,
                    CheckEnabled    =>  TRUE,
                    Violation       =>  Pviol_CLKLIn );

               VitalPeriodPulseCheck (
                    TestSignal      =>  CLKRIn,
                    TestSignalName  =>  "CLKR",
                    Period          =>  tperiod_CLKR,
                    PulseWidthLow   =>  tpw_CLKR,
                    PulseWidthHigh  =>  tpw_CLKR,
                    PeriodData      =>  TD_CLKRIn,
                    XOn             =>  XOn,
                    MsgOn           =>  MsgOn,
                    HeaderMsg       =>  InstancePath & PartID,
                    CheckEnabled    =>  TRUE,
                    Violation       =>  Pviol_CLKRIn );

               Violation := Tviol_ALIn_CLKLIn OR Tviol_ARIn_CLKRIn OR
                            Tviol_CLKENLNegIn_CLKLIn OR Tviol_CLKENRNegIn_CLKRIn
                            OR Pviol_CLKLIn OR Pviol_CLKRIn;

            END IF; -- Timing Check Section

            --------------------------------------------------------------------
            -- Functional Section
            --------------------------------------------------------------------

            IF rising_edge(CLKLIn) THEN
                IF CELNeg_nwv = '0' THEN 
                    IF CLKENLNeg_nwv = '0' THEN     -- Load address
                        LocationL := To_Nat(ALIn);
                        LastLocL := LocationL;
                    ELSE
                        LocationL := LastLocL;
                    END IF;
                    IF RWL_nwv = '1' THEN   -- Read 
                        IF CLKENLNeg_nwv = '1' THEN   --DataOut No Change
                            DataLTmp := DataLastL;
                        ELSE
                            DataTempL := MemData0(LocationL);
                            IF DataTempL >= 0 THEN
                                DataLTmp := To_slv(DataTempL, DataWidth);
                            ELSIF DataTempL = -2 THEN
                                DataLTmp := (OTHERS => 'U');
                            ELSE
                                DataLTmp := (OTHERS => 'X');
                            END IF;
                            DataLastL := DataLTmp;
                        END IF;
                    ELSE    -- Write
                        DataLtmp := (OTHERS => 'Z');
                        IF Violation = '0' AND CLKENLNeg_nwv = '0' THEN
                            MemData0(LocationL) := To_Nat(IOLIn);
                        ELSE
                            MemData1(LocationL):= -1;
                        END IF;
                    END IF;
                ELSE
                    DataLtmp := (OTHERS => 'Z');
                END IF;
            END IF;
            
            IF rising_edge(CLKRIn) THEN
                IF CERNeg_nwv = '0' THEN 
                    IF CLKENRNeg_nwv = '0' THEN     -- Load address
                        LocationR := To_Nat(ARIn);
                        LastLocR := LocationR;
                    ELSE
                        LocationR := LastLocR;
                    END IF;
                    IF RWR_nwv = '1' THEN   -- Read 
                        IF CLKENRNeg_nwv = '1' THEN   --DataOut No Change
                            DataRTmp := DataLastR;
                        ELSE
                            DataTempR := MemData1(LocationR);
                            IF DataTempR >= 0 THEN
                                DataRTmp := To_slv(DataTempR, DataWidth);
                            ELSIF DataTempR = -2 THEN
                                DataRTmp := (OTHERS => 'U');
                            ELSE
                                DataRTmp := (OTHERS => 'X');
                            END IF;
                            DataLastR := DataRTmp;
                        END IF;
                    ELSE    -- Write
                        DataRtmp := (OTHERS => 'Z');
                        IF Violation = '0' AND CLKENRNeg_nwv = '0' THEN
                            MemData1(LocationR) := To_Nat(IORIn);
                        ELSE
                            MemData0(LocationR):= -1;
                        END IF;
                    END IF;
                ELSE
                    DataRtmp := (OTHERS => 'Z');
                END IF;
            END IF;
            IF OELNeg_nwv = '1' THEN
                DataLDrive := (OTHERS => 'Z');
            ELSE
                DataLDrive := DataLTmp;
            END IF;
            IF OERNeg_nwv = '1' THEN
                DataRDrive := (OTHERS => 'Z');
            ELSE
                DataRDrive := DataRTmp;
            END IF;

            IOL_zd <= DataLDrive;
            IOR_zd <= DataRDrive;
        END PROCESS Memory;

        ------------------------------------------------------------------------
        -- Path Delay Processes generated as a function of data width
        ------------------------------------------------------------------------
        DataOut_Width : FOR i IN HiDbit DOWNTO 0 GENERATE
            DataOut_Delay : PROCESS (IOR_zd(i), IOL_zd(i))
             VARIABLE IOR_GlitchData:VitalGlitchDataArrayType(HiDbit Downto 0);
             VARIABLE IOL_GlitchData:VitalGlitchDataArrayType(HiDbit Downto 0);
            BEGIN
                VitalPathDelay01Z (
                    OutSignal       => IOLOut(i),
                    OutSignalName   => "IOL",
                    OutTemp         => IOL_zd(i),
                    Mode            => OnEvent,
                    GlitchData      => IOL_GlitchData(i),
                    Paths           => (
                        0 => (InputChangeTime => OELNegIn'LAST_EVENT,
                              PathDelay       => tpd_OERNeg_IOR0,
                              PathCondition   => TRUE),
                        1 => (InputChangeTime => CLKLIn'LAST_EVENT,
                              PathDelay       => tpd_CLKR_IOR0,
                              PathCondition   => TRUE)
                   )
               );

                VitalPathDelay01Z (
                    OutSignal       => IOROut(i),
                    OutSignalName   => "IOR",
                    OutTemp         => IOR_zd(i),
                    Mode            => OnEvent,
                    GlitchData      => IOR_GlitchData(i),
                    Paths           => (
                        0 => (InputChangeTime => OERNegIn'LAST_EVENT,
                              PathDelay       => tpd_OERNeg_IOR0,
                              PathCondition   => TRUE),
                        1 => (InputChangeTime => CLKRIn'LAST_EVENT,
                              PathDelay       => tpd_CLKR_IOR0,
                              PathCondition   => TRUE)
                   )
               );
            END PROCESS DataOut_Delay;
        END GENERATE;
    
    END BLOCK;
END vhdl_behavioral;