idt70914.vhd

vhdl cod for ram.For sp3e

    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (RWR_ipd, RWR, tipd_RWR);
        w_2 : VitalWireDelay (RWL_ipd, RWL, tipd_RWL);
        w_3 : VitalWireDelay (CERNeg_ipd, CERNeg, tipd_CERNeg);
        w_4 : VitalWireDelay (CELNeg_ipd, CELNeg, tipd_CELNeg);
        w_5 : VitalWireDelay (CLKR_ipd, CLKR, tipd_CLKR);
        w_6 : VitalWireDelay (CLKL_ipd, CLKL, tipd_CLKL);
        w_7 : VitalWireDelay (OERNeg_ipd, OERNeg, tipd_OERNeg);
        w_8 : VitalWireDelay (OELNeg_ipd, OELNeg, tipd_OELNeg);
        w_9 : VitalWireDelay (AR0_ipd, AR0, tipd_AR0);
        w_10 : VitalWireDelay (AR1_ipd, AR1, tipd_AR1);
        w_11 : VitalWireDelay (AR2_ipd, AR2, tipd_AR2);
        w_12 : VitalWireDelay (AR3_ipd, AR3, tipd_AR3);
        w_13 : VitalWireDelay (AR4_ipd, AR4, tipd_AR4);
        w_14 : VitalWireDelay (AR5_ipd, AR5, tipd_AR5);
        w_15 : VitalWireDelay (AR6_ipd, AR6, tipd_AR6);
        w_16 : VitalWireDelay (AR7_ipd, AR7, tipd_AR7);
        w_17 : VitalWireDelay (AR8_ipd, AR8, tipd_AR8);
        w_18 : VitalWireDelay (AR9_ipd, AR9, tipd_AR9);
        w_19 : VitalWireDelay (AR10_ipd, AR10, tipd_AR10);
        w_20 : VitalWireDelay (AR11_ipd, AR11, tipd_AR11);
        w_21 : VitalWireDelay (AL0_ipd, AL0, tipd_AL0);
        w_22 : VitalWireDelay (AL1_ipd, AL1, tipd_AL1);
        w_23 : VitalWireDelay (AL2_ipd, AL2, tipd_AL2);
        w_24 : VitalWireDelay (AL3_ipd, AL3, tipd_AL3);
        w_25 : VitalWireDelay (AL4_ipd, AL4, tipd_AL4);
        w_26 : VitalWireDelay (AL5_ipd, AL5, tipd_AL5);
        w_27 : VitalWireDelay (AL6_ipd, AL6, tipd_AL6);
        w_28 : VitalWireDelay (AL7_ipd, AL7, tipd_AL7);
        w_29 : VitalWireDelay (AL8_ipd, AL8, tipd_AL8);
        w_30 : VitalWireDelay (AL9_ipd, AL9, tipd_AL9);
        w_31 : VitalWireDelay (AL10_ipd, AL10, tipd_AL10);
        w_32 : VitalWireDelay (AL11_ipd, AL11, tipd_AL11);
        w_33 : VitalWireDelay (IOR8_ipd, IOR8, tipd_IOR8);
        w_34 : VitalWireDelay (IOR7_ipd, IOR7, tipd_IOR7);
        w_35 : VitalWireDelay (IOR6_ipd, IOR6, tipd_IOR6);
        w_36 : VitalWireDelay (IOR5_ipd, IOR5, tipd_IOR5);
        w_37 : VitalWireDelay (IOR4_ipd, IOR4, tipd_IOR4);
        w_38 : VitalWireDelay (IOR3_ipd, IOR3, tipd_IOR3);
        w_39 : VitalWireDelay (IOR2_ipd, IOR2, tipd_IOR2);
        w_40 : VitalWireDelay (IOR1_ipd, IOR1, tipd_IOR1);
        w_41 : VitalWireDelay (IOR0_ipd, IOR0, tipd_IOR0);
        w_42 : VitalWireDelay (IOL8_ipd, IOL8, tipd_IOL8);
        w_43 : VitalWireDelay (IOL7_ipd, IOL7, tipd_IOL7);
        w_44 : VitalWireDelay (IOL6_ipd, IOL6, tipd_IOL6);
        w_45 : VitalWireDelay (IOL5_ipd, IOL5, tipd_IOL5);
        w_46 : VitalWireDelay (IOL4_ipd, IOL4, tipd_IOL4);
        w_47 : VitalWireDelay (IOL3_ipd, IOL3, tipd_IOL3);
        w_48 : VitalWireDelay (IOL2_ipd, IOL2, tipd_IOL2);
        w_49 : VitalWireDelay (IOL1_ipd, IOL1, tipd_IOL1);
        w_50 : VitalWireDelay (IOL0_ipd, IOL0, tipd_IOL0);
        w_51 : VitalWireDelay (CLKENRNeg_ipd, CLKENRNeg, tipd_CLKENRNeg);
        w_52 : VitalWireDelay (CLKENLNeg_ipd, CLKENLNeg, tipd_CLKENLNeg);
       
    END BLOCK;

    ----------------------------------------------------------------------------
    -- Main Behavior Block
    ----------------------------------------------------------------------------
    Behavior: BLOCK

        PORT (
            ALIn         : IN    std_logic_vector(HiAbit downto 0);
            ARIn         : IN    std_logic_vector(HiAbit downto 0);
            IOLIn        : IN    std_logic_vector(HiDbit downto 0);
            IORIn        : IN    std_logic_vector(HiDbit downto 0);
            IOLOut       : OUT   std_logic_vector(HiDbit downto 0);
            IOROut       : OUT   std_logic_vector(HiDbit downto 0);
            OERNegIn     : IN    std_ulogic := 'U';
            OELNegIn     : IN    std_ulogic := 'U';
            CLKRIn       : IN    std_ulogic := 'U';
            CLKLIn       : IN    std_ulogic := 'U';
            CLKENRNegIn  : IN    std_ulogic := 'U';
            CLKENLNegIn  : IN    std_ulogic := 'U';
            RWRIn        : IN    std_ulogic := 'U';
            RWLIn        : IN    std_ulogic := 'U';
            CERNegIn     : IN    std_ulogic := 'U';
            CELNegIn     : IN    std_ulogic := 'U'
        );
        PORT MAP (
            ALIn(0) =>  AL0_ipd,
            ALIn(1) =>  AL1_ipd,
            ALIn(2) =>  AL2_ipd,
            ALIn(3) =>  AL3_ipd,
            ALIn(4) =>  AL4_ipd,
            ALIn(5) =>  AL5_ipd,
            ALIn(6) =>  AL6_ipd,
            ALIn(7) =>  AL7_ipd,
            ALIn(8) =>  AL8_ipd,
            ALIn(9) =>  AL9_ipd,
            ALIn(10) =>  AL10_ipd,
            ALIn(11) =>  AL11_ipd,
            ARIn(0) =>  AR0_ipd,
            ARIn(1) =>  AR1_ipd,
            ARIn(2) =>  AR2_ipd,
            ARIn(3) =>  AR3_ipd,
            ARIn(4) =>  AR4_ipd,
            ARIn(5) =>  AR5_ipd,
            ARIn(6) =>  AR6_ipd,
            ARIn(7) =>  AR7_ipd,
            ARIn(8) =>  AR8_ipd,
            ARIn(9) =>  AR9_ipd,
            ARIn(10) =>  AR10_ipd,
            ARIn(11) =>  AR11_ipd,
            IOLIn(0) => IOL0_ipd,
            IOLIn(1) => IOL1_ipd,
            IOLIn(2) => IOL2_ipd,
            IOLIn(3) => IOL3_ipd,
            IOLIn(4) => IOL4_ipd,
            IOLIn(5) => IOL5_ipd,
            IOLIn(6) => IOL6_ipd,
            IOLIn(7) => IOL7_ipd,
            IOLIn(8) => IOL8_ipd,
            IORIn(0) => IOR0_ipd,
            IORIn(1) => IOR1_ipd,
            IORIn(2) => IOR2_ipd,
            IORIn(3) => IOR3_ipd,
            IORIn(4) => IOR4_ipd,
            IORIn(5) => IOR5_ipd,
            IORIn(6) => IOR6_ipd,
            IORIn(7) => IOR7_ipd,
            IORIn(8) => IOR8_ipd,
            IOROut(0) => IOR0,
            IOROut(1) => IOR1,
            IOROut(2) => IOR2,
            IOROut(3) => IOR3,
            IOROut(4) => IOR4,
            IOROut(5) => IOR5,
            IOROut(6) => IOR6,
            IOROut(7) => IOR7,
            IOROut(8) => IOR8,
            IOLOut(0) => IOL0,
            IOLOut(1) => IOL1,
            IOLOut(2) => IOL2,
            IOLOut(3) => IOL3,
            IOLOut(4) => IOL4,
            IOLOut(5) => IOL5,
            IOLOut(6) => IOL6,
            IOLOut(7) => IOL7,
            IOLOut(8) => IOL8,
            OELNegIn  => OELNeg_ipd,
            OERNegIn  => OERNeg_ipd,
            CLKLIn   => CLKL_ipd,
            CLKRIn   => CLKR_ipd,
            CLKENLNegIn  => CLKENLNeg_ipd,
            CLKENRNegIn  => CLKENRNeg_ipd,
            RWLIn    => RWL_ipd,
            RWRIn    => RWR_ipd,
            CELNegIn  => CELNeg_ipd,
            CERNegIn  => CERNeg_ipd
        );

        SIGNAL IOL_zd       : std_logic_vector(HiDbit DOWNTO 0);
        SIGNAL IOR_zd       : std_logic_vector(HiDbit DOWNTO 0);

    BEGIN
        ------------------------------------------------------------------------
        -- Behavior Process
        ------------------------------------------------------------------------
        Memory : PROCESS (OELNegIn, OERNegIn, RWLIn, RWRIn, CELNegIn,
                          CERNegIn, ALIn, ARIn, IOLIn, IORIn,
                          CLKLIn, CLKRIn, CLKENLNegIn, CLKENRNegIn)

            -- Timing Check Variables
            VARIABLE Tviol_ALIn_CLKLIn         : X01 := '0';
            VARIABLE TD_ALIn_CLKLIn            : VitalTimingDataType;

            VARIABLE Tviol_ARIn_CLKRIn         : X01 := '0';
            VARIABLE TD_ARIn_CLKRIn            : VitalTimingDataType;

            VARIABLE Tviol_CLKENLNegIn_CLKLIn  :  X01 := '0';
            VARIABLE TD_CLKENLNegIn_CLKLIn     : VitalTimingDataType;

            VARIABLE Tviol_CLKENRNegIn_CLKRIn  :  X01 := '0';
            VARIABLE TD_CLKENRNegIn_CLKRIn     : VitalTimingDataType;

            VARIABLE Pviol_CLKLIn              :  X01 := '0';
            VARIABLE TD_CLKLIn     : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Pviol_CLKRIn              :  X01 := '0';
            VARIABLE TD_CLKRIn     : VitalPeriodDataType := VitalPeriodDataInit;

            -- Functionality Results Variables
            VARIABLE Violation  : X01 := '0';

            -- Memory array declaration
            TYPE MemStore IS ARRAY (0 to TotalLOC) OF INTEGER
                             RANGE  -2 TO MaxData;

            VARIABLE DataLDrive  : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE DataRDrive  : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');

            VARIABLE DataLTmp    : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE DataLastL   : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');

            VARIABLE DataRTmp    : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE DataLastR   : std_logic_vector(HiDbit DOWNTO 0)
                                   := (OTHERS => 'Z');

            VARIABLE MemData0    : MemStore;
            VARIABLE MemData1    : MemStore;
            VARIABLE DataTempL   : INTEGER RANGE -2 TO MaxData := -2;
            VARIABLE DataTempR   : INTEGER RANGE -2 TO MaxData := -2;
            VARIABLE LocationL   : NATURAL RANGE 0 TO TotalLOC := 0;
            VARIABLE LocationR   : NATURAL RANGE 0 TO TotalLOC := 0;
            VARIABLE LastLocL    : NATURAL RANGE 0 TO TotalLOC := 0;
            VARIABLE LastLocR    : NATURAL RANGE 0 TO TotalLOC := 0;

            -- No Weak Values Variables
            VARIABLE CELNeg_nwv        : UX01 := 'U';
            VARIABLE CERNeg_nwv        : UX01 := 'U';
            VARIABLE RWR_nwv           : UX01 := 'U';
            VARIABLE RWL_nwv           : UX01 := 'U';
            VARIABLE OELNeg_nwv        : UX01 := 'U';
            VARIABLE OERNeg_nwv        : UX01 := 'U';
            VARIABLE CLKENLNeg_nwv     : UX01 := 'U';
            VARIABLE CLKENRNeg_nwv     : UX01 := 'U';

        BEGIN
            CELNeg_nwv     := To_UX01 (s => CELNegIn);
            CERNeg_nwv     := To_UX01 (s => CERNegIn);
            RWL_nwv        := To_UX01 (s => RWLIn);
            RWR_nwv        := To_UX01 (s => RWRIn);
            OELNeg_nwv     := To_UX01 (s => OELNegIn);
            OERNeg_nwv     := To_UX01 (s => OERNegIn);
            CLKENLNeg_nwv  := To_UX01 (s => CLKENLNegIn);
            CLKENRNeg_nwv  := To_UX01 (s => CLKENRNegIn);