idt70914.vhd

vhdl cod for ram.For sp3e

--------------------------------------------------------------------------------
--  File Name: idt70914.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2001 Free Model Foundry; http://www.FreeModelFoundry.com
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--------------------------------------------------------------------------------
--  MODIFICATION HISTORY:
-- 
--  version: |       author:        | mod date: | changes made:
--    V1.0     S.Randjic D.Djokovic   01 OCT 18   Initial release
-- 
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:    RAM
--  Technology: CMOS
--  Part:       IDT70914
-- 
--  Description: Synchronous Dual Port RAM 4K x 9
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;
                USE FMF.conversions.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY idt70914 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_IOR8                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR7                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR6                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR5                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR4                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR3                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR2                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR1                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOR0                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL8                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL7                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL6                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL5                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL4                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL3                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL2                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL1                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOL0                : VitalDelayType01 := VitalZeroDelay01;
        tipd_OERNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_OELNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_CLKR                : VitalDelayType01 := VitalZeroDelay01;
        tipd_CLKL                : VitalDelayType01 := VitalZeroDelay01;
        tipd_CLKENRNeg           : VitalDelayType01 := VitalZeroDelay01;
        tipd_CLKENLNeg           : VitalDelayType01 := VitalZeroDelay01;
        tipd_RWR                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_RWL                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_CERNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_CELNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR0                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR1                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR2                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR3                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR4                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR5                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR6                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR7                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR8                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR9                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR10                : VitalDelayType01 := VitalZeroDelay01;
        tipd_AR11                : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL0                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL1                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL2                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL3                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL4                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL5                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL6                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL7                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL8                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL9                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL10                : VitalDelayType01 := VitalZeroDelay01;
        tipd_AL11                : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        -- tCD, tCKLZ, tCKHZ
        tpd_CLKR_IOR0            : VitalDelayType01Z := UnitDelay01Z;
        tpd_OERNeg_IOR0          : VitalDelayType01Z := UnitDelay01Z;
        -- tpw values: pulse widths
        tpw_CLKR                 : VitalDelayType    := UnitDelay;
        -- tperiod_min: minimum clock period = 1/max freq
        tperiod_CLKR             : VitalDelayType := UnitDelay;
        -- tsetup values: setup times
        tsetup_AR0_CLKR          : VitalDelayType    := UnitDelay;
        tsetup_CLKENRNeg_CLKR    : VitalDelayType    := UnitDelay;
        -- thold values: hold times
        thold_AR0_CLKR           : VitalDelayType    := UnitDelay;
        thold_CLKENRNeg_CLKR     : VitalDelayType    := UnitDelay;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        IOR8            : INOUT std_ulogic := 'U';
        IOR7            : INOUT std_ulogic := 'U';
        IOR6            : INOUT std_ulogic := 'U';
        IOR5            : INOUT std_ulogic := 'U';
        IOR4            : INOUT std_ulogic := 'U';
        IOR3            : INOUT std_ulogic := 'U';
        IOR2            : INOUT std_ulogic := 'U';
        IOR1            : INOUT std_ulogic := 'U';
        IOR0            : INOUT std_ulogic := 'U';
        IOL8            : INOUT std_ulogic := 'U';
        IOL7            : INOUT std_ulogic := 'U';
        IOL6            : INOUT std_ulogic := 'U';
        IOL5            : INOUT std_ulogic := 'U';
        IOL4            : INOUT std_ulogic := 'U';
        IOL3            : INOUT std_ulogic := 'U';
        IOL2            : INOUT std_ulogic := 'U';
        IOL1            : INOUT std_ulogic := 'U';
        IOL0            : INOUT std_ulogic := 'U';
        OERNeg          : IN    std_ulogic := 'U';
        OELNeg          : IN    std_ulogic := 'U';
        CLKR            : IN    std_ulogic := 'U';
        CLKL            : IN    std_ulogic := 'U';
        CLKENRNeg       : IN    std_ulogic := 'U';
        CLKENLNeg       : IN    std_ulogic := 'U';
        RWR             : IN    std_ulogic := 'U';
        RWL             : IN    std_ulogic := 'U';
        CERNeg          : IN    std_ulogic := 'U';
        CELNeg          : IN    std_ulogic := 'U';
        AR0             : IN    std_ulogic := 'U';
        AR1             : IN    std_ulogic := 'U';
        AR2             : IN    std_ulogic := 'U';
        AR3             : IN    std_ulogic := 'U';
        AR4             : IN    std_ulogic := 'U';
        AR5             : IN    std_ulogic := 'U';
        AR6             : IN    std_ulogic := 'U';
        AR7             : IN    std_ulogic := 'U';
        AR8             : IN    std_ulogic := 'U';
        AR9             : IN    std_ulogic := 'U';
        AR10            : IN    std_ulogic := 'U';
        AR11            : IN    std_ulogic := 'U';
        AL0             : IN    std_ulogic := 'U';
        AL1             : IN    std_ulogic := 'U';
        AL2             : IN    std_ulogic := 'U';
        AL3             : IN    std_ulogic := 'U';
        AL4             : IN    std_ulogic := 'U';
        AL5             : IN    std_ulogic := 'U';
        AL6             : IN    std_ulogic := 'U';
        AL7             : IN    std_ulogic := 'U';
        AL8             : IN    std_ulogic := 'U';
        AL9             : IN    std_ulogic := 'U';
        AL10            : IN    std_ulogic := 'U';
        AL11            : IN    std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of idt70914 : ENTITY IS TRUE;
END idt70914;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of idt70914 IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT partID         : STRING := "IDT70914";
    CONSTANT MaxData        : NATURAL := 511;
    CONSTANT TotalLOC       : NATURAL := 36863;
    CONSTANT HiAbit         : NATURAL := 11;
    CONSTANT HiDbit         : NATURAL := 8;
    CONSTANT DataWidth      : NATURAL := 9;    
 
    SIGNAL IOR8_ipd         : std_ulogic := 'U';
    SIGNAL IOR7_ipd         : std_ulogic := 'U';
    SIGNAL IOR6_ipd         : std_ulogic := 'U';
    SIGNAL IOR5_ipd         : std_ulogic := 'U';
    SIGNAL IOR4_ipd         : std_ulogic := 'U';
    SIGNAL IOR3_ipd         : std_ulogic := 'U';
    SIGNAL IOR2_ipd         : std_ulogic := 'U';
    SIGNAL IOR1_ipd         : std_ulogic := 'U';
    SIGNAL IOR0_ipd         : std_ulogic := 'U';
    SIGNAL IOL8_ipd         : std_ulogic := 'U';
    SIGNAL IOL7_ipd         : std_ulogic := 'U';
    SIGNAL IOL6_ipd         : std_ulogic := 'U';
    SIGNAL IOL5_ipd         : std_ulogic := 'U';
    SIGNAL IOL4_ipd         : std_ulogic := 'U';
    SIGNAL IOL3_ipd         : std_ulogic := 'U';
    SIGNAL IOL2_ipd         : std_ulogic := 'U';
    SIGNAL IOL1_ipd         : std_ulogic := 'U';
    SIGNAL IOL0_ipd         : std_ulogic := 'U';
    SIGNAL OERNeg_ipd       : std_ulogic := 'U';
    SIGNAL OELNeg_ipd       : std_ulogic := 'U';
    SIGNAL CLKR_ipd         : std_ulogic := 'U';
    SIGNAL CLKL_ipd         : std_ulogic := 'U';
    SIGNAL CLKENRNeg_ipd    : std_ulogic := 'U';
    SIGNAL CLKENLNeg_ipd    : std_ulogic := 'U';
    SIGNAL RWR_ipd          : std_ulogic := 'U';
    SIGNAL RWL_ipd          : std_ulogic := 'U';
    SIGNAL CERNeg_ipd       : std_ulogic := 'U';
    SIGNAL CELNeg_ipd       : std_ulogic := 'U';
    SIGNAL AR0_ipd          : std_ulogic := 'U';
    SIGNAL AR1_ipd          : std_ulogic := 'U';
    SIGNAL AR2_ipd          : std_ulogic := 'U';
    SIGNAL AR3_ipd          : std_ulogic := 'U';
    SIGNAL AR4_ipd          : std_ulogic := 'U';
    SIGNAL AR5_ipd          : std_ulogic := 'U';
    SIGNAL AR6_ipd          : std_ulogic := 'U';
    SIGNAL AR7_ipd          : std_ulogic := 'U';
    SIGNAL AR8_ipd          : std_ulogic := 'U';
    SIGNAL AR9_ipd          : std_ulogic := 'U';
    SIGNAL AR10_ipd         : std_ulogic := 'U';
    SIGNAL AR11_ipd         : std_ulogic := 'U';
    SIGNAL AL0_ipd          : std_ulogic := 'U';
    SIGNAL AL1_ipd          : std_ulogic := 'U';
    SIGNAL AL2_ipd          : std_ulogic := 'U';
    SIGNAL AL3_ipd          : std_ulogic := 'U';
    SIGNAL AL4_ipd          : std_ulogic := 'U';
    SIGNAL AL5_ipd          : std_ulogic := 'U';
    SIGNAL AL6_ipd          : std_ulogic := 'U';
    SIGNAL AL7_ipd          : std_ulogic := 'U';
    SIGNAL AL8_ipd          : std_ulogic := 'U';
    SIGNAL AL9_ipd          : std_ulogic := 'U';
    SIGNAL AL10_ipd         : std_ulogic := 'U';
    SIGNAL AL11_ipd         : std_ulogic := 'U';

BEGIN

    ----------------------------------------------------------------------------