📄 idt71v65803.ftm
字号:
<!DOCTYPE FTML SYSTEM "ftml.dtd"><FTML><HEAD><TITLE>FMF Timing for IDT71V65803 Parts</TITLE><REVISION.HISTORY>version: | author: | mod date: | changes made: V1.0 R. Munden 02 NOV 02 Initial release</REVISION.HISTORY></HEAD><BODY><TIMESCALE>1ns</TIMESCALE><MODEL>IDT71V65803<FMFTIME>IDT71V65803S150BG<SOURCE>IDT Datasheet DSC-5304/04 Rev. October 2001</SOURCE>IDT71V65803S150BQ<SOURCE>IDT Datasheet DSC-5304/04 Rev. October 2001</SOURCE>IDT71V65803S150PF<SOURCE>IDT Datasheet DSC-5304/04 Rev. October 2001</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, Ta=0 to +70 Celsius</COMMENT><COMMENT>For each parameter only min or max values were supplied by vendor - all others were derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.5:3.0:3.8) (1.5:3.0:3.8) (1.5:2.6:3.0) (1.5:3.0:3.8) (1.5:2.6:3.0) (1.5:3.0:3.8)) (IOPATH OENeg DQA0 () () (0.0:3.0:3.8) (0.0:3.0:3.8) (0.0:3.0:3.8) (0.0:3.0:3.8)) )) (TIMINGCHECK (WIDTH (posedge CLK) (2.0)) (WIDTH (negedge CLK) (2.0)) (PERIOD (posedge CLK) (6.7)) (SETUP CLKENNeg CLK (1.5)) (SETUP A0 CLK (1.5)) (SETUP DQA0 CLK (1.5)) (SETUP R CLK (1.5)) (SETUP ADV CLK (1.5)) (SETUP CE2 CLK (1.5)) (SETUP BWANeg CLK (1.5)) (HOLD CLKENNeg CLK (0.5)) (HOLD A0 CLK (0.5)) (HOLD DQA0 CLK (0.5)) (HOLD R CLK (0.5)) (HOLD ADV CLK (0.5)) (HOLD CE2 CLK (0.5)) (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>IDT71V65803S133BG<SOURCE>IDT Datasheet DSC-5304/04 Rev. October 2001</SOURCE>IDT71V65803S133BQ<SOURCE>IDT Datasheet DSC-5304/04 Rev. October 2001</SOURCE>IDT71V65803S133PF<SOURCE>IDT Datasheet DSC-5304/04 Rev. October 2001</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, Ta=0 to +70 Celsius</COMMENT><COMMENT>For each parameter only min or max values were supplied by vendor - all others were derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.5:3.3:4.2) (1.5:3.3:4.2) (1.5:2.6:3.0) (1.5:3.4:4.2) (1.5:2.6:3.0) (1.5:3.4:4.2)) (IOPATH OENeg DQA0 () () (0.0:3.6:4.2) (0.0:3.6:4.2) (0.0:3.6:4.2) (0.0:3.6:4.2)) )) (TIMINGCHECK (WIDTH (posedge CLK) (2.2)) (WIDTH (negedge CLK) (2.2)) (PERIOD (posedge CLK) (7.5)) (SETUP CLKENNeg CLK (1.7)) (SETUP A0 CLK (1.7)) (SETUP DQA0 CLK (1.7)) (SETUP R CLK (1.7)) (SETUP ADV CLK (1.7)) (SETUP CE2 CLK (1.7)) (SETUP BWANeg CLK (1.7)) (HOLD CLKENNeg CLK (0.5)) (HOLD A0 CLK (0.5)) (HOLD DQA0 CLK (0.5)) (HOLD R CLK (0.5)) (HOLD ADV CLK (0.5)) (HOLD CE2 CLK (0.5)) (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>IDT71V65803S100BG<SOURCE>IDT Datasheet DSC-5304/04 Rev. October 2001</SOURCE>IDT71V65803S100BQ<SOURCE>IDT Datasheet DSC-5304/04 Rev. October 2001</SOURCE>IDT71V65803S100PF<SOURCE>IDT Datasheet DSC-5304/04 Rev. October 2001</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, Ta=0 to +70 Celsius</COMMENT><COMMENT>For each parameter only min or max values were supplied by vendor - all others were derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.5:3.8:5.0) (1.5:3.8:5.0) (1.5:2.4:3.3) (1.5:3.8:5.0) (1.5:2.4:3.3) (1.5:3.8:5.0)) (IOPATH OENeg DQA0 () () (0.0:3.0:5.0) (0.0:3.0:5.0) (0.0:3.0:5.0) (0.0:3.0:5.0)) )) (TIMINGCHECK (WIDTH (posedge CLK) (3.2)) (WIDTH (negedge CLK) (3.2)) (PERIOD (posedge CLK) (10.0)) (SETUP CLKENNeg CLK (2.0)) (SETUP A0 CLK (2.0)) (SETUP DQA0 CLK (2.0)) (SETUP R CLK (2.0)) (SETUP ADV CLK (2.0)) (SETUP CE2 CLK (2.0)) (SETUP BWANeg CLK (2.0)) (HOLD CLKENNeg CLK (0.5)) (HOLD A0 CLK (0.5)) (HOLD DQA0 CLK (0.5)) (HOLD R CLK (0.5)) (HOLD ADV CLK (0.5)) (HOLD CE2 CLK (0.5)) (HOLD BWANeg CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>MT55L512L18PB-10<SOURCE>Micron Technology MT55L512L18P_C.p65 - Rev. 2/02</SOURCE>MT55L512L18PF-10<SOURCE>Micron Technology MT55L512L18P_C.p65 - Rev. 2/02</SOURCE>MT55L512L18PT-10<SOURCE>Micron Technology MT55L512L18P_C.p65 - Rev. 2/02</SOURCE>MT55L512V18PB-10<SOURCE>Micron Technology MT55L512L18P_C.p65 - Rev. 2/02</SOURCE>MT55L512V18PF-10<SOURCE>Micron Technology MT55L512L18P_C.p65 - Rev. 2/02</SOURCE>MT55L512V18PT-10<SOURCE>Micron Technology MT55L512L18P_C.p65 - Rev. 2/02</SOURCE><COMMENT> The values listed are for VCC=3.3V, CL=50pF, Ta=0 to +70 Celsius</COMMENT><COMMENT>For each parameter only min or max values were supplied by vendor - all others were derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.5:3:5) (1.5:3:5) (1.5:2.5:3.5) (1.5:3:5) (1.5:2.5:3.5) (1.5:3:5)) (IOPATH OENeg DQA0 () () (1.5:3:5) (0:3:5) (1.5:3:5) (0:3:5)) )) (TIMINGCHECK (SETUP CLKENNeg CLK (2:2:2)) (SETUP A0 CLK (2:2:2)) (SETUP DQA0 CLK (2:2:2)) (SETUP R CLK (2:2:2)) (SETUP ADV CLK (2:2:2)) (SETUP CE2 CLK (2:2:2)) (SETUP BWANeg CLK (2:2:2)) (HOLD CLKENNeg CLK (.5:.5:.5)) (HOLD A0 CLK (.5:.5:.5)) (HOLD DQA0 CLK (.5:.5:.5)) (HOLD R CLK (.5:.5:.5)) (HOLD ADV CLK (.5:.5:.5)) (HOLD CE2 CLK (.5:.5:.5)) (HOLD BWANeg CLK (.5:.5:.5)) (WIDTH (posedge CLK) (3.2:3.2:3.2)) (WIDTH (negedge CLK) (3.2:3.2:3.2)) (PERIOD (posedge CLK) (10:10:10)) )</TIMING></FMFTIME><FMFTIME>MT55L512L18PB-7.5<SOURCE>Micron Technology MT55L512L18P_C.p65 - Rev. 2/02</SOURCE>MT55L512L18PF-7.5<SOURCE>Micron Technology MT55L512L18P_C.p65 - Rev. 2/02</SOURCE>MT55L512L18PT-7.5<SOURCE>Micron Technology MT55L512L18P_C.p65 - Rev. 2/02</SOURCE>MT55L512V18PB-7.5<SOURCE>Micron Technology MT55L512L18P_C.p65 - Rev. 2/02</SOURCE>MT55L512V18PF-7.5<SOURCE>Micron Technology MT55L512L18P_C.p65 - Rev. 2/02</SOURCE>MT55L512V18PT-7.5<SOURCE>Micron Technology MT55L512L18P_C.p65 - Rev. 2/02</SOURCE><COMMENT> The values listed are for VCC=3.3V, CL=50pF, Ta=0 to +70 Celsius</COMMENT><COMMENT>For each parameter only min or max values were supplied by vendor - all others were derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.5:2.8:4.2) (1.5:2.8:4.2) (1.5:2.5:3.5) (1.5:2.8:4.2) (1.5:2.5:3.5) (1.5:2.8:4.2)) (IOPATH OENeg DQA0 () () (1.5:2.8:4.2) (0:2.8:4.2) (1.5:2.8:4.2) (0:2.8:4.2)) )) (TIMINGCHECK (SETUP CLKENNeg CLK (1.7:1.7:1.7)) (SETUP A0 CLK (1.7:1.7:1.7)) (SETUP DQA0 CLK (1.7:1.7:1.7)) (SETUP R CLK (1.7:1.7:1.7)) (SETUP ADV CLK (1.7:1.7:1.7)) (SETUP CE2 CLK (1.7:1.7:1.7)) (SETUP BWANeg CLK (1.7:1.7:1.7)) (HOLD CLKENNeg CLK (.5:.5:.5)) (HOLD A0 CLK (.5:.5:.5)) (HOLD DQA0 CLK (.5:.5:.5)) (HOLD R CLK (.5:.5:.5)) (HOLD ADV CLK (.5:.5:.5)) (HOLD CE2 CLK (.5:.5:.5)) (HOLD BWANeg CLK (.5:.5:.5)) (WIDTH (posedge CLK) (2:2:2)) (WIDTH (negedge CLK) (2:2:2)) (PERIOD (posedge CLK) (7.5:7.5:7.5)) )</TIMING></FMFTIME><FMFTIME>MT55L512L18PB-6<SOURCE>Micron Technology MT55L512L18P_C.p65 - Rev. 2/02</SOURCE>MT55L512L18PF-6<SOURCE>Micron Technology MT55L512L18P_C.p65 - Rev. 2/02</SOURCE>MT55L512L18PT-6<SOURCE>Micron Technology MT55L512L18P_C.p65 - Rev. 2/02</SOURCE>MT55L512V18PB-6<SOURCE>Micron Technology MT55L512L18P_C.p65 - Rev. 2/02</SOURCE>MT55L512V18PF-6<SOURCE>Micron Technology MT55L512L18P_C.p65 - Rev. 2/02</SOURCE>MT55L512V18PT-6<SOURCE>Micron Technology MT55L512L18P_C.p65 - Rev. 2/02</SOURCE><COMMENT> The values listed are for VCC=3.3V, CL=50pF, Ta=0 to +70 Celsius</COMMENT><COMMENT>For each parameter only min or max values were supplied by vendor - all others were derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.5:2.5:3.5) (1.5:2.5:3.5) (1.5:2.5:3.5) (1.5:2.5:3.5) (1.5:2.5:3.5) (1.5:2.5:3.5)) (IOPATH OENeg DQA0 () () (1.5:2.5:3.5) (0:2.5:3.5) (1.5:2.5:3.5) (0:2.5:3.5)) )) (TIMINGCHECK (SETUP CLKENNeg CLK (1.5:1.5:1.5)) (SETUP A0 CLK (1.5:1.5:1.5)) (SETUP DQA0 CLK (1.5:1.5:1.5)) (SETUP R CLK (1.5:1.5:1.5)) (SETUP ADV CLK (1.5:1.5:1.5)) (SETUP CE2 CLK (1.5:1.5:1.5)) (SETUP BWANeg CLK (1.5:1.5:1.5)) (HOLD CLKENNeg CLK (.5:.5:.5)) (HOLD A0 CLK (.5:.5:.5)) (HOLD DQA0 CLK (.5:.5:.5)) (HOLD R CLK (.5:.5:.5)) (HOLD ADV CLK (.5:.5:.5)) (HOLD CE2 CLK (.5:.5:.5)) (HOLD BWANeg CLK (.5:.5:.5)) (WIDTH (posedge CLK) (1.7:1.7:1.7)) (WIDTH (negedge CLK) (1.7:1.7:1.7)) (PERIOD (posedge CLK) (6:6:6)) )</TIMING></FMFTIME><FMFTIME>CY7C1356B-166AC<SOURCE>Cypress Semiconductor 38-05114 August 16, 2002</SOURCE>CY7C1356B-166BGC<SOURCE>Cypress Semiconductor 38-05114 August 16, 2002</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, Ta=0 to +70 Celsius</COMMENT><COMMENT>For each parameter only min or max values were supplied by vendor - all others were derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.5:2.4:3.5) (1.5:2.4:3.5) (1.5:2.5:3.5) (1.5:2.4:3.6) (1.5:2.5:3.5) (1.5:2.4:3.6)) (IOPATH OENeg DQA0 () () (1:2.3:3.5) (0:2.4:3.5) (1:2.3:3.5) (0:2.4:3.5)) )) (TIMINGCHECK (SETUP CLKENNeg CLK (1.5:1.5:1.5)) (SETUP A0 CLK (1.5:1.5:1.5)) (SETUP DQA0 CLK (1.5:1.5:1.5)) (SETUP R CLK (1.5:1.5:1.5)) (SETUP ADV CLK (1.5:1.5:1.5)) (SETUP CE2 CLK (1.5:1.5:1.5)) (SETUP BWANeg CLK (1.5:1.5:1.5)) (HOLD CLKENNeg CLK (.5:.5:.5)) (HOLD A0 CLK (.5:.5:.5)) (HOLD DQA0 CLK (.5:.5:.5)) (HOLD R CLK (.5:.5:.5)) (HOLD ADV CLK (.5:.5:.5)) (HOLD CE2 CLK (.5:.5:.5)) (HOLD BWANeg CLK (.5:.5:.5)) (WIDTH (posedge CLK) (2.4)) (WIDTH (negedge CLK) (2.4)) (PERIOD (posedge CLK) (6:6:6)) )</TIMING></FMFTIME><FMFTIME>CY7C1356B-200AC<SOURCE>Cypress Semiconductor 38-05114 August 16, 2002</SOURCE>CY7C1356B-200BGC<SOURCE>Cypress Semiconductor 38-05114 August 16, 2002</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, Ta=0 to +70 Celsius</COMMENT><COMMENT>For each parameter only min or max values were supplied by vendor - all others were derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.5:2.1:3.0) (1.5:2.1:3.0) (1.5:2:3) (1.5:2.1:3.0) (1.5:2:3) (1.5:2.1:3.0)) (IOPATH OENeg DQA0 () () (1:2.3:3.0) (0:2.1:3.0) (1:2.3:3.0) (0:2.1:3.0)) )) (TIMINGCHECK (SETUP CLKENNeg CLK (1.5:1.5:1.5)) (SETUP A0 CLK (1.5:1.5:1.5)) (SETUP DQA0 CLK (1.5:1.5:1.5)) (SETUP R CLK (1.5:1.5:1.5)) (SETUP ADV CLK (1.5:1.5:1.5)) (SETUP CE2 CLK (1.5:1.5:1.5)) (SETUP BWANeg CLK (1.5:1.5:1.5)) (HOLD CLKENNeg CLK (.5:.5:.5)) (HOLD A0 CLK (.5:.5:.5)) (HOLD DQA0 CLK (.5:.5:.5)) (HOLD R CLK (.5:.5:.5)) (HOLD ADV CLK (.5:.5:.5)) (HOLD CE2 CLK (.5:.5:.5)) (HOLD BWANeg CLK (.5:.5:.5)) (WIDTH (posedge CLK) (2.0)) (WIDTH (negedge CLK) (2.0)) (PERIOD (posedge CLK) (5:5:5)) )</TIMING></FMFTIME><FMFTIME>CY7C1356B-250AC<SOURCE>Cypress Semiconductor 38-05114 August 16, 2002</SOURCE>CY7C1356B-250BGC<SOURCE>Cypress Semiconductor 38-05114 August 16, 2002</SOURCE><COMMENT> The values listed are for VCC=3.135V to 3.465V, Ta=0 to +70 Celsius</COMMENT><COMMENT>For each parameter only min or max values were supplied by vendor - all others were derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.25:2.0:2.6) (1.25:2.0:2.6) (1.25:2:2.6) (1.25:2.1:2.6) (1.25:2:2.6) (1.25:2.1:2.6)) (IOPATH OENeg DQA0 () () (1:2.0:2.6) (0:2.0:2.6) (1:2.0:2.6) (0:2.0:2.6)) )) (TIMINGCHECK (SETUP CLKENNeg CLK (1.2)) (SETUP A0 CLK (1.2)) (SETUP DQA0 CLK (1.2)) (SETUP R CLK (1.2)) (SETUP ADV CLK (1.2)) (SETUP CE2 CLK (1.2)) (SETUP BWANeg CLK (1.2)) (HOLD CLKENNeg CLK (.3)) (HOLD A0 CLK (.3)) (HOLD DQA0 CLK (.3)) (HOLD R CLK (.3)) (HOLD ADV CLK (.3)) (HOLD CE2 CLK (.3)) (HOLD BWANeg CLK (.3)) (WIDTH (posedge CLK) (1.7)) (WIDTH (negedge CLK) (1.7)) (PERIOD (posedge CLK) (4)) )</TIMING></FMFTIME></BODY></FTML>⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -