mt4lc4m16r6.vhd

vhdl cod for ram.For sp3e

                    Removal         => tremoval_WENeg_RASNeg,
                    ActiveLow       => TRUE,
                    CheckEnabled    => CBR,
                    RefTransition   => '\',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_WE_RAS,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_WE_RAS );

                -- tWCS, tWCH
                VitalRecoveryRemovalCheck (
                    TestSignal      => WENegIn,
                    TestSignalName  => "WENeg",
                    RefSignal       => CASLIn,
                    RefSignalName   => "CASL",
                    Recovery        => trecovery_WENeg_CASLNeg,
                    Removal         => tremoval_WENeg_CASLNeg,
                    ActiveLow       => TRUE,
                    CheckEnabled    => (write = early),
                    RefTransition   => '\',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_WE_CASL,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_WE_CASL );

                -- tWCS, tWCH
                VitalRecoveryRemovalCheck (
                    TestSignal      => WENegIn,
                    TestSignalName  => "WENeg",
                    RefSignal       => CASHIn,
                    RefSignalName   => "CASH",
                    Recovery        => trecovery_WENeg_CASLNeg,
                    Removal         => tremoval_WENeg_CASLNeg,
                    ActiveLow       => TRUE,
                    CheckEnabled    => (write = early),
                    RefTransition   => '\',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_WE_CASH,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_WE_CASH );

                -- tCSR, tCHR
                VitalRecoveryRemovalCheck (
                    TestSignal      => CASLIn,
                    TestSignalName  => "CASL",
                    RefSignal       => RASNegIn,
                    RefSignalName   => "RASNeg",
                    Recovery        => trecovery_CASLNeg_RASNeg,
                    Removal         => tremoval_CASLNeg_RASNeg,
                    ActiveLow       => TRUE,
                    CheckEnabled    => CBR,
                    RefTransition   => '\',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_CASL_RAS,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_CASL_RAS );

                -- tCSR, tCHR
                VitalRecoveryRemovalCheck (
                    TestSignal      => CASHIn,
                    TestSignalName  => "CASH",
                    RefSignal       => RASNegIn,
                    RefSignalName   => "RASNeg",
                    Recovery        => trecovery_CASLNeg_RASNeg,
                    Removal         => tremoval_CASLNeg_RASNeg,
                    ActiveLow       => TRUE,
                    CheckEnabled    => CBR,
                    RefTransition   => '\',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_CASH_RAS,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_CASH_RAS );

                -- tRAS, tRP
                VitalPeriodPulseCheck (
                    TestSignal      =>  RASNegIn,
                    TestSignalName  =>  "RASNeg",
                    PulseWidthLow   =>  tpw_RASNeg_negedge,
                    PulseWidthHigh  =>  tpw_RASNeg_posedge,
                    PeriodData      =>  PD_RAS,
                    XOn             =>  XOn,
                    MsgOn           =>  MsgOn,
                    Violation       =>  Pviol_RAS,
                    HeaderMsg       =>  InstancePath & PartID,
                    CheckEnabled    =>  TRUE );

                -- tCAS, tCP
                VitalPeriodPulseCheck (
                    TestSignal      =>  CASLIn,
                    TestSignalName  =>  "CASLNeg",
                    PulseWidthLow   =>  tpw_CASLNeg_negedge,
                    PulseWidthHigh  =>  tpw_CASLNeg_posedge,
                    PeriodData      =>  PD_CASL,
                    XOn             =>  XOn,
                    MsgOn           =>  MsgOn,
                    Violation       =>  Pviol_CASL,
                    HeaderMsg       =>  InstancePath & PartID,
                    CheckEnabled    =>  TRUE );

                -- tCAS, tCP
                VitalPeriodPulseCheck (
                    TestSignal      =>  CASHIn,
                    TestSignalName  =>  "CASHNeg",
                    PulseWidthLow   =>  tpw_CASLNeg_negedge,
                    PulseWidthHigh  =>  tpw_CASLNeg_posedge,
                    PeriodData      =>  PD_CASH,
                    XOn             =>  XOn,
                    MsgOn           =>  MsgOn,
                    Violation       =>  Pviol_CASH,
                    HeaderMsg       =>  InstancePath & PartID,
                    CheckEnabled    =>  TRUE );

                -- tWP
                VitalPeriodPulseCheck (
                    TestSignal      =>  WENegIn,
                    TestSignalName  =>  "WENeg",
                    PulseWidthLow   =>  tpw_WENeg_negedge,
                    PeriodData      =>  PD_WE,
                    XOn             =>  XOn,
                    MsgOn           =>  MsgOn,
                    Violation       =>  Pviol_WE,
                    HeaderMsg       =>  InstancePath & PartID,
                    CheckEnabled    =>  TRUE );

                Violation := Tviol_Address_CASL OR Tviol_Address_CASH OR
                             Tviol_Address_RAS OR Pviol_CASL OR Pviol_CASH
                             OR Tviol_CASL_RAS OR Tviol_CASH_RAS OR
                             Tviol_WE_RAS OR Pviol_WE OR Pviol_RAS OR
                             Tviol_DataH_WE OR Tviol_DataL_WE OR 
                             Tviol_Data_CASL OR Tviol_Data_CASH OR
                             Tviol_WE_CASH OR Tviol_WE_CASL;

                ASSERT Violation = '0'
                    REPORT InstancePath & partID & ": simulation may be" &
                           " inaccurate due to timing violations"
                    SEVERITY SeverityMode;

            END IF; -- Timing Check Section

    --------------------------------------------------------------------
    -- Functional Section
    --------------------------------------------------------------------

        cas := VitalAND2(a => CASHIn, b => CASLIn);

        IF (NOW > Next_Ref AND PoweredUp = true AND Ref_Cnt > 0) THEN
            Ref_Cnt := Ref_Cnt - 1;
            Next_Ref := NOW + tdevice_REF;
        END IF;

        IF (falling_edge(RASNegIn)) THEN
            IF (CASHIn = '0' AND CASLIn = '0') THEN
                IF (WENegIn = '1') THEN
                    CBR := TRUE;
                    Ref_Cnt := Ref_Cnt + 1;
                    IF (not(ready) AND PoweredUp AND Ref_Cnt = 8) THEN
                        ready := TRUE;
                    END IF;
                ELSE
                    ASSERT FALSE
                        REPORT InstancePath & partID & ": Unknown operation;"
                               & " WENeg must be high for CBR"
                        SEVERITY SeverityMode;
                END IF;
            ELSIF (cas = '1') THEN
                ASSERT (not(Is_X(AddressIn)))
                    REPORT InstancePath & partID & ": Unusable value for address"
                    SEVERITY SeverityMode;
                MemAddr(21 downto 10) := AddressIn;
                CBR := FALSE;
            END IF;
        END IF;

        IF ((falling_edge(CASHIn) OR falling_edge(CASLIn)) AND RASNegIn = '0') THEN
            ASSERT (not(Is_X(WENegIn)))
                REPORT InstancePath & partID & ": Unusable value for WENeg"
                SEVERITY SeverityMode;
            ASSERT (not(Is_X(AddressIn)))
                REPORT InstancePath & partID & ": Unusable value for address"
                SEVERITY SeverityMode;
            MemAddr(9 downto 0) := AddressIn(9 downto 0);
            Location := to_nat(MemAddr);
            -- Read Cycle
            IF (WENegIn = '1') THEN
                IF (CASHIn = '0') THEN
                    DataDriveH := to_slv(MemH(Location),8);
                END IF;
                IF (CASLIn = '0') THEN
                    DataDriveL := to_slv(MemL(Location),8);
                END IF;

            -- Early Write Cycle
            ELSE
                ASSERT ready
                    REPORT InstancePath & partID & ": memory is not ready for"
                                 & " use - must be powered up and refreshed" 
                    SEVERITY SeverityMode;
                IF (CASHIn = '0') THEN
                    MemH(Location) := to_nat(DataInH);
                END IF;
                IF (CASLIn = '0') THEN
                    MemL(Location) := to_nat(DataInL);
                END IF;
                written := true;
                write := early;
            END IF;
        END IF;

        IF (falling_edge(WENegIn)) THEN
            DataDriveL := (others => 'Z');
            DataDriveH := (others => 'Z');
            -- Late Write Cycle
            IF (RASNegIn = '0') THEN
                ASSERT ready
                    REPORT InstancePath & partID & ": memory is not ready for"
                                 & " use - must be powered up and refreshed" 
                    SEVERITY SeverityMode;
                IF (CASHIn = '0') THEN
                    MemH(Location) := to_nat(DataInH);
                END IF;
                IF (CASLIn = '0') THEN
                    MemL(Location) := to_nat(DataInL);
                END IF;
                written := true;
                write := late;
            END IF;
        END IF;

    -- Check Refresh Status
        IF (written = true) THEN
            ASSERT Ref_Cnt > 0
                REPORT InstancePath & partID &
                       ": memory not refreshed (by ref_cnt)"
                SEVERITY SeverityMode;
            IF (Ref_Cnt < 1) THEN
                ready := FALSE;
            END IF;
        END IF;

        --------------------------------------------------------------------
        -- Output Section
        --------------------------------------------------------------------
        IF (OENegIn = '0' AND (cas = '0' OR RASNegIn = '0')) THEN
            DH_zd <= DataDriveH;
            DL_zd <= DataDriveL;
        ELSE
            DH_zd <= (others => 'Z');
            DL_zd <= (others => 'Z');
        END IF;

        END PROCESS;

        ------------------------------------------------------------------------
        -- Path Delay Process
        ------------------------------------------------------------------------
        DataOutLBlk : FOR i IN 7 DOWNTO 0 GENERATE
            DataOut_Delay : PROCESS (DL_zd(i))
                VARIABLE DL_GlitchData:VitalGlitchDataArrayType(7 Downto 0);
            BEGIN
                VitalPathDelay01Z (
                    OutSignal       => DataOutL(i),
                    OutSignalName   => "DataL",
                    OutTemp         => DL_zd(i),
                    Mode            => OnEvent,
                    GlitchData      => DL_GlitchData(i),
                    Paths           => (
                        1 => (InputChangeTime => CASLIn'LAST_EVENT,
                              PathDelay => tpd_CASLNeg_IO0,
                              PathCondition   => CASLIn = '0'),
                        2 => (InputChangeTime => OENegIn'LAST_EVENT,
                              PathDelay => tpd_OENeg_IO0,
                              PathCondition   => TRUE),
                        3 => (InputChangeTime => WENegIn'LAST_EVENT,
                              PathDelay => tpd_WENeg_IO0,
                              PathCondition   => TRUE),
                        4 => (InputChangeTime => CASLIn'LAST_EVENT,
                              PathDelay => tpd_RASNeg_IO0, -- tOFF
                              PathCondition   => RASNegIn = '1' AND CASLIn = '1'),
                        5 => (InputChangeTime => RASNegIn'LAST_EVENT,
                              PathDelay => tpd_RASNeg_IO0, -- tOFF
                              PathCondition   => RASNegIn = '1' AND CASLIn = '1')
                   )
                );

            END PROCESS;
        END GENERATE;

        DataOutHBlk : FOR i IN 7 DOWNTO 0 GENERATE
            DataOut_Delay : PROCESS (DH_zd(i))
                VARIABLE DH_GlitchData:VitalGlitchDataArrayType(7 Downto 0);
            BEGIN
                VitalPathDelay01Z (
                    OutSignal       => DataOutH(i),
                    OutSignalName   => "DataH",
                    OutTemp         => DH_zd(i),
                    Mode            => OnEvent,
                    GlitchData      => DH_GlitchData(i),
                    Paths           => (
                        1 => (InputChangeTime => CASHIn'LAST_EVENT,
                              PathDelay => tpd_CASLNeg_IO0,
                              PathCondition   => TRUE),
                        2 => (InputChangeTime => OENegIn'LAST_EVENT,
                              PathDelay => tpd_OENeg_IO0,
                              PathCondition   => TRUE),
                        3 => (InputChangeTime => WENegIn'LAST_EVENT,
                              PathDelay => tpd_WENeg_IO0,
                              PathCondition   => TRUE),
                        4 => (InputChangeTime => CASHIn'LAST_EVENT,
                              PathDelay => tpd_RASNeg_IO0, -- tOFF
                              PathCondition   => RASNegIn = '1' AND CASHIn = '1'),
                        5 => (InputChangeTime => RASNegIn'LAST_EVENT,
                              PathDelay => tpd_RASNeg_IO0, -- tOFF
                              PathCondition   => RASNegIn = '1' AND CASHIn = '1')
                   )
                );

            END PROCESS;
        END GENERATE;

    END BLOCK;

END vhdl_behavioral;