mt4lc4m16r6.vhd

vhdl cod for ram.For sp3e

    IO7_nwv <= To_UX01(IO7_ipd);
    IO8_nwv <= To_UX01(IO8_ipd);
    IO9_nwv <= To_UX01(IO9_ipd);
    IO10_nwv <= To_UX01(IO10_ipd);
    IO11_nwv <= To_UX01(IO11_ipd);
    IO12_nwv <= To_UX01(IO12_ipd);
    IO13_nwv <= To_UX01(IO13_ipd);
    IO14_nwv <= To_UX01(IO14_ipd);
    IO15_nwv <= To_UX01(IO15_ipd);
    A0_nwv <= To_UX01(A0_ipd);
    A1_nwv <= To_UX01(A1_ipd);
    A2_nwv <= To_UX01(A2_ipd);
    A3_nwv <= To_UX01(A3_ipd);
    A4_nwv <= To_UX01(A4_ipd);
    A5_nwv <= To_UX01(A5_ipd);
    A6_nwv <= To_UX01(A6_ipd);
    A7_nwv <= To_UX01(A7_ipd);
    A8_nwv <= To_UX01(A8_ipd);
    A9_nwv <= To_UX01(A9_ipd);
    A10_nwv <= To_UX01(A10_ipd);
    A11_nwv <= To_UX01(A11_ipd);

    ----------------------------------------------------------------------------
    -- Main Behavior Block
    ----------------------------------------------------------------------------
    Behavior: BLOCK

        PORT (
            CASLIn          : IN    std_ulogic := 'X';
            CASHIn          : IN    std_ulogic := 'X';
            DataInH         : IN    std_logic_vector(7 downto 0);
            DataInL         : IN    std_logic_vector(7 downto 0);
            DataOutH        : OUT   std_logic_vector(7 downto 0)
                                                     := (others => 'Z');
            DataOutL        : OUT   std_logic_vector(7 downto 0)
                                                     := (others => 'Z');
            AddressIn       : IN    std_logic_vector(11 downto 0);
            WENegIn         : IN    std_ulogic := 'X';
            RASNegIn        : IN    std_ulogic := 'X';
            OENegIn         : IN    std_ulogic := 'X'
        );
        PORT MAP (
            CASLIn => CASLNeg_nwv,
            CASHIn => CASHNeg_nwv,
            DataOutL(0) =>  IO0,
            DataOutL(1) =>  IO1,
            DataOutL(2) =>  IO2,
            DataOutL(3) =>  IO3,
            DataOutL(4) =>  IO4,
            DataOutL(5) =>  IO5,
            DataOutL(6) =>  IO6,
            DataOutL(7) =>  IO7,
            DataOutH(0) =>  IO8,
            DataOutH(1) =>  IO9,
            DataOutH(2) =>  IO10,
            DataOutH(3) =>  IO11,
            DataOutH(4) =>  IO12,
            DataOutH(5) =>  IO13,
            DataOutH(6) =>  IO14,
            DataOutH(7) =>  IO15,
            DataInL(0) =>  IO0_nwv,
            DataInL(1) =>  IO1_nwv,
            DataInL(2) =>  IO2_nwv,
            DataInL(3) =>  IO3_nwv,
            DataInL(4) =>  IO4_nwv,
            DataInL(5) =>  IO5_nwv,
            DataInL(6) =>  IO6_nwv,
            DataInL(7) =>  IO7_nwv,
            DataInH(0) =>  IO8_nwv,
            DataInH(1) =>  IO9_nwv,
            DataInH(2) =>  IO10_nwv,
            DataInH(3) =>  IO11_nwv,
            DataInH(4) =>  IO12_nwv,
            DataInH(5) =>  IO13_nwv,
            DataInH(6) =>  IO14_nwv,
            DataInH(7) =>  IO15_nwv,
            AddressIn(0) => A0_nwv,
            AddressIn(1) => A1_nwv,
            AddressIn(2) => A2_nwv,
            AddressIn(3) => A3_nwv,
            AddressIn(4) => A4_nwv,
            AddressIn(5) => A5_nwv,
            AddressIn(6) => A6_nwv,
            AddressIn(7) => A7_nwv,
            AddressIn(8) => A8_nwv,
            AddressIn(9) => A9_nwv,
            AddressIn(10) => A10_nwv,
            AddressIn(11) => A11_nwv,
            WENegIn => WENeg_nwv,
            RASNegIn => RASNeg_nwv,
            OENegIn => OENeg_nwv
        );

        SIGNAL DH_zd     : std_logic_vector(7 DOWNTO 0);
        SIGNAL DL_zd     : std_logic_vector(7 DOWNTO 0);

    BEGIN

    PoweredUp <= true after tpowerup;

    ----------------------------------------------------------------------------
    -- Main Behavior Process
    ----------------------------------------------------------------------------
        Behavior : PROCESS (CASLIn, CASHIn, DataInH, DataInL, AddressIn,
                            WENegIn, RASNegIn, OENegIn)

            -- Timing Check Variables
            VARIABLE Tviol_Address_CASL  : X01 := '0';
            VARIABLE TD_Address_CASL     : VitalTimingDataType;

            VARIABLE Tviol_Address_CASH  : X01 := '0';
            VARIABLE TD_Address_CASH     : VitalTimingDataType;

            VARIABLE Tviol_Address_RAS   : X01 := '0';
            VARIABLE TD_Address_RAS      : VitalTimingDataType;

            VARIABLE Tviol_Data_CASL     : X01 := '0';
            VARIABLE TD_Data_CASL        : VitalTimingDataType;

            VARIABLE Tviol_Data_CASH     : X01 := '0';
            VARIABLE TD_Data_CASH        : VitalTimingDataType;

            VARIABLE Tviol_DataH_WE      : X01 := '0';
            VARIABLE TD_DataH_WE         : VitalTimingDataType;

            VARIABLE Tviol_DataL_WE      : X01 := '0';
            VARIABLE TD_DataL_WE         : VitalTimingDataType;

            VARIABLE Tviol_WE_RAS        : X01 := '0';
            VARIABLE TD_WE_RAS           : VitalTimingDataType;

            VARIABLE Tviol_WE_CASL       : X01 := '0';
            VARIABLE TD_WE_CASL          : VitalTimingDataType;

            VARIABLE Tviol_WE_CASH       : X01 := '0';
            VARIABLE TD_WE_CASH          : VitalTimingDataType;

            VARIABLE Tviol_CASL_RAS      : X01 := '0';
            VARIABLE TD_CASL_RAS         : VitalTimingDataType;

            VARIABLE Tviol_CASH_RAS      : X01 := '0';
            VARIABLE TD_CASH_RAS         : VitalTimingDataType;

            VARIABLE Pviol_CASH    : X01 := '0';
            VARIABLE PD_CASH       : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Pviol_CASL    : X01 := '0';
            VARIABLE PD_CASL       : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Pviol_WE      : X01 := '0';
            VARIABLE PD_WE         : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Pviol_RAS     : X01 := '0';
            VARIABLE PD_RAS        : VitalPeriodDataType := VitalPeriodDataInit;

            -- Functionality Results Variables
            VARIABLE Violation  : X01 := '0';
            VARIABLE DataDriveH   :  std_logic_vector(7 DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE DataDriveL   :  std_logic_vector(7 DOWNTO 0)
                                   := (OTHERS => 'Z');

            -- Type definition for wirtes
            TYPE write_type is (early,
                                late
                               );

            VARIABLE write      : write_type;

            -- Memory array declaration
            TYPE MemStore IS ARRAY (0 to 4194303) OF NATURAL
                             RANGE  0 TO 255;

            VARIABLE MemH       : MemStore;
            VARIABLE MemL       : MemStore;

            VARIABLE MemAddr    : std_logic_vector(21 DOWNTO 0)
                                   := (OTHERS => 'X');
            VARIABLE Location     : NATURAL RANGE 0 TO 4194303 := 0;

            VARIABLE CBR        : boolean := FALSE;

            VARIABLE Ref_Cnt      : NATURAL RANGE 0 TO 4096 := 1;
            VARIABLE next_ref     : TIME;

            VARIABLE cas        : UX01 := 'U';
            VARIABLE written    : boolean := false;
            VARIABLE ready      : boolean := false;

        BEGIN

            --------------------------------------------------------------------
            -- Timing Check Section
            --------------------------------------------------------------------
            IF (TimingChecksOn) THEN

                -- tASC, tCAH
                VitalSetupHoldCheck (
                    TestSignal      => AddressIn,
                    TestSignalName  => "Address",
                    RefSignal       => CASLIn,
                    RefSignalName   => "CASL",
                    SetupHigh       => tsetup_A0_CASLNeg,
                    SetupLow        => tsetup_A0_CASLNeg,
                    HoldHigh        => thold_A0_CASLNeg,
                    HoldLow         => thold_A0_CASLNeg,
                    CheckEnabled    => (RASNegIn ='0'),
                    RefTransition   => '\',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_Address_CASL,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_Address_CASL );

                -- tASC, tCAH
                VitalSetupHoldCheck (
                    TestSignal      => AddressIn,
                    TestSignalName  => "Address",
                    RefSignal       => CASHIn,
                    RefSignalName   => "CASH",
                    SetupHigh       => tsetup_A0_CASLNeg,
                    SetupLow        => tsetup_A0_CASLNeg,
                    HoldHigh        => thold_A0_CASLNeg,
                    HoldLow         => thold_A0_CASLNeg,
                    CheckEnabled    => (RASNegIn ='0'),
                    RefTransition   => '\',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_Address_CASH,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_Address_CASH );

                -- tASR, tRAH
                VitalSetupHoldCheck (
                    TestSignal      => AddressIn,
                    TestSignalName  => "Address",
                    RefSignal       => RASNegIn,
                    RefSignalName   => "RASNeg",
                    SetupHigh       => tsetup_A0_RASNeg,
                    SetupLow        => tsetup_A0_RASNeg,
                    HoldHigh        => thold_A0_RASNeg,
                    HoldLow         => thold_A0_RASNeg,
                    CheckEnabled    => (CASLIn = '1' AND CASHIn = '1'),
                    RefTransition   => '\',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_Address_RAS,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_Address_RAS );

                -- tDS, tDH
                VitalSetupHoldCheck (
                    TestSignal      => DataInH,
                    TestSignalName  => "DataInH",
                    RefSignal       => CASHIn,
                    RefSignalName   => "CASH",
                    SetupHigh       => tsetup_IO0_WENeg,
                    SetupLow        => tsetup_IO0_WENeg,
                    HoldHigh        => thold_IO0_WENeg,
                    HoldLow         => thold_IO0_WENeg,
                    CheckEnabled    => (write = early),
                    RefTransition   => '\',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_Data_CASH,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_Data_CASH );

                -- tDS, tDH
                VitalSetupHoldCheck (
                    TestSignal      => DataInL,
                    TestSignalName  => "DataInL",
                    RefSignal       => CASLIn,
                    RefSignalName   => "CASL",
                    SetupHigh       => tsetup_IO0_WENeg,
                    SetupLow        => tsetup_IO0_WENeg,
                    HoldHigh        => thold_IO0_WENeg,
                    HoldLow         => thold_IO0_WENeg,
                    CheckEnabled    => (write = early),
                    RefTransition   => '\',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_Data_CASL,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_Data_CASL );

                -- tDS, tDH
                VitalSetupHoldCheck (
                    TestSignal      => DataInL,
                    TestSignalName  => "DataInL",
                    RefSignal       => WENegIn,
                    RefSignalName   => "WENeg",
                    SetupHigh       => tsetup_IO0_WENeg,
                    SetupLow        => tsetup_IO0_WENeg,
                    HoldHigh        => thold_IO0_WENeg,
                    HoldLow         => thold_IO0_WENeg,
                    CheckEnabled    => (write = late),
                    RefTransition   => '\',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_DataL_WE,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_DataL_WE );

                -- tDS, tDH
                VitalSetupHoldCheck (
                    TestSignal      => DataInH,
                    TestSignalName  => "DataInH",
                    RefSignal       => WENegIn,
                    RefSignalName   => "WENeg",
                    SetupHigh       => tsetup_IO0_WENeg,
                    SetupLow        => tsetup_IO0_WENeg,
                    HoldHigh        => thold_IO0_WENeg,
                    HoldLow         => thold_IO0_WENeg,
                    CheckEnabled    => (write = late),
                    RefTransition   => '\',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_DataH_WE,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_DataH_WE );

                -- tWRP, tWRH
                VitalRecoveryRemovalCheck (
                    TestSignal      => WENegIn,
                    TestSignalName  => "WENeg",
                    RefSignal       => RASNegIn,
                    RefSignalName   => "RASNeg",
                    Recovery        => trecovery_WENeg_RASNeg,