mt4lc4m16r6.vhd

vhdl cod for ram.For sp3e

--------------------------------------------------------------------------------
--  File Name: mt4lc4m16r6.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1999-2003 Free Model Foundry; http://www.FreeModelFoundry.com
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0    R. Munden    99 AUG 23   Initial release
--    V1.1    R. Munden    00 FEB 07   Changed type of cas to UX01
--    V1.2    R. Munden    02 APR 04   Corrected type used with VitalBuf
--    V1.3    R. Munden    03 MAR 15   Changed type of some _nwv signals to
--                                     satisfy ncvhdl
-- 
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:    RAM
--  Technology: DRAM
--  Part:       MT4LC4M16R6
-- 
--  Description: EDO DRAM 4M x 16
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;
                USE FMF.conversions.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY mt4lc4m16r6 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_IO15                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO14                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO13                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO12                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO11                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO10                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO9                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO8                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO7                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO6                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO5                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO4                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO3                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO2                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO1                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_IO0                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A0                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A1                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A2                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A3                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A4                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A5                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A6                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A7                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A8                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A9                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A10                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A11                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_CASLNeg             : VitalDelayType01 := VitalZeroDelay01;
        tipd_CASHNeg             : VitalDelayType01 := VitalZeroDelay01;
        tipd_RASNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_WENeg               : VitalDelayType01 := VitalZeroDelay01;
        tipd_OENeg               : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        --    tAA
        tpd_A0_IO0               : VitalDelayType01Z := UnitDelay01Z;
        --    tCAC, tCLZ, tCOH, tOFF
        tpd_CASLNeg_IO0          : VitalDelayType01Z := UnitDelay01Z;
        --    tRAC, tOFF
        tpd_RASNeg_IO0           : VitalDelayType01Z := UnitDelay01Z;
        --    tOE, tOD
        tpd_OENeg_IO0            : VitalDelayType01Z := UnitDelay01Z;
        --    tWHZ
        tpd_WENeg_IO0            : VitalDelayType01Z := UnitDelay01Z;

        -- tpw values: pulse widths
        --    tCP
        tpw_CASLNeg_posedge          : VitalDelayType    := UnitDelay;
        --    tWP
        tpw_WENeg_negedge            : VitalDelayType    := UnitDelay;
        --    tCAS
        tpw_CASLNeg_negedge          : VitalDelayType    := UnitDelay;
        --    tRAS
        tpw_RASNeg_negedge           : VitalDelayType    := UnitDelay;
        --    tRP
        tpw_RASNeg_posedge           : VitalDelayType    := UnitDelay;

        -- tsetup values: setup times
        --    tASC
        tsetup_A0_CASLNeg        : VitalDelayType    := UnitDelay;
        --    tASR
        tsetup_A0_RASNeg         : VitalDelayType    := UnitDelay;
        --    tDS
        tsetup_IO0_WENeg         : VitalDelayType    := UnitDelay;

        -- thold values: hold times
        --    tRAH
        thold_A0_RASNeg          : VitalDelayType    := UnitDelay;
        --    tCAH
        thold_A0_CASLNeg         : VitalDelayType    := UnitDelay;
        --    tDH
        thold_IO0_WENeg          : VitalDelayType    := UnitDelay;

        -- trecovery values: setup times
        --    tCSR
        trecovery_CASLNeg_RASNeg : VitalDelayType    := UnitDelay;
        --    tCWD
        trecovery_CASLNeg_WENeg  : VitalDelayType    := UnitDelay;
        --    tWRP
        trecovery_WENeg_RASNeg   : VitalDelayType    := UnitDelay;
        --    tWCS
        trecovery_WENeg_CASLNeg  : VitalDelayType    := UnitDelay;

        -- tremoval values: hold times
        --    tCHR
        tremoval_CASLNeg_RASNeg  : VitalDelayType    := UnitDelay;
        --    tWRH
        tremoval_WENeg_RASNeg    : VitalDelayType    := UnitDelay;
        --    tWCH
        tremoval_WENeg_CASLNeg   : VitalDelayType    := UnitDelay;

        -- tdevice values: values for internal delays
        -- time between refresh
        tdevice_REF              : VitalDelayType    := 15_625 ns;

        -- tpowerup: Power up initialization time. Data sheets say 100-200 us.
        -- May be shortened during simulation debug.
        tpowerup            : TIME      := 100 us;

        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        SeverityMode        : SEVERITY_LEVEL := WARNING;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        IO15            : INOUT std_logic := 'U';
        IO14            : INOUT std_logic := 'U';
        IO13            : INOUT std_logic := 'U';
        IO12            : INOUT std_logic := 'U';
        IO11            : INOUT std_logic := 'U';
        IO10            : INOUT std_logic := 'U';
        IO9             : INOUT std_logic := 'U';
        IO8             : INOUT std_logic := 'U';
        IO7             : INOUT std_logic := 'U';
        IO6             : INOUT std_logic := 'U';
        IO5             : INOUT std_logic := 'U';
        IO4             : INOUT std_logic := 'U';
        IO3             : INOUT std_logic := 'U';
        IO2             : INOUT std_logic := 'U';
        IO1             : INOUT std_logic := 'U';
        IO0             : INOUT std_logic := 'U';
        A0              : IN    std_logic := 'U';
        A1              : IN    std_logic := 'U';
        A2              : IN    std_logic := 'U';
        A3              : IN    std_logic := 'U';
        A4              : IN    std_logic := 'U';
        A5              : IN    std_logic := 'U';
        A6              : IN    std_logic := 'U';
        A7              : IN    std_logic := 'U';
        A8              : IN    std_logic := 'U';
        A9              : IN    std_logic := 'U';
        A10             : IN    std_logic := 'U';
        A11             : IN    std_logic := 'U';
        CASLNeg         : IN    std_logic := 'U';
        CASHNeg         : IN    std_logic := 'U';
        RASNeg          : IN    std_logic := 'U';
        WENeg           : IN    std_logic := 'U';
        OENeg           : IN    std_logic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of mt4lc4m16r6 : ENTITY IS TRUE;
END mt4lc4m16r6;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of mt4lc4m16r6 IS
    ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS FALSE;

    CONSTANT partID            : STRING := "mt4lc4m16r6";

    SIGNAL PoweredUp           : boolean := false;

    SIGNAL IO15_ipd            : std_ulogic := 'X';
    SIGNAL IO14_ipd            : std_ulogic := 'X';
    SIGNAL IO13_ipd            : std_ulogic := 'X';
    SIGNAL IO12_ipd            : std_ulogic := 'X';
    SIGNAL IO11_ipd            : std_ulogic := 'X';
    SIGNAL IO10_ipd            : std_ulogic := 'X';
    SIGNAL IO9_ipd             : std_ulogic := 'X';
    SIGNAL IO8_ipd             : std_ulogic := 'X';
    SIGNAL IO7_ipd             : std_ulogic := 'X';
    SIGNAL IO6_ipd             : std_ulogic := 'X';
    SIGNAL IO5_ipd             : std_ulogic := 'X';
    SIGNAL IO4_ipd             : std_ulogic := 'X';
    SIGNAL IO3_ipd             : std_ulogic := 'X';
    SIGNAL IO2_ipd             : std_ulogic := 'X';
    SIGNAL IO1_ipd             : std_ulogic := 'X';
    SIGNAL IO0_ipd             : std_ulogic := 'X';
    SIGNAL A0_ipd              : std_ulogic := 'X';
    SIGNAL A1_ipd              : std_ulogic := 'X';
    SIGNAL A2_ipd              : std_ulogic := 'X';
    SIGNAL A3_ipd              : std_ulogic := 'X';
    SIGNAL A4_ipd              : std_ulogic := 'X';
    SIGNAL A5_ipd              : std_ulogic := 'X';
    SIGNAL A6_ipd              : std_ulogic := 'X';
    SIGNAL A7_ipd              : std_ulogic := 'X';
    SIGNAL A8_ipd              : std_ulogic := 'X';
    SIGNAL A9_ipd              : std_ulogic := 'X';
    SIGNAL A10_ipd             : std_ulogic := 'X';
    SIGNAL A11_ipd             : std_ulogic := 'X';
    SIGNAL CASLNeg_ipd         : std_ulogic := 'X';
    SIGNAL CASHNeg_ipd         : std_ulogic := 'X';
    SIGNAL RASNeg_ipd          : std_ulogic := 'X';
    SIGNAL WENeg_ipd           : std_ulogic := 'X';
    SIGNAL OENeg_ipd           : std_ulogic := 'X';

    SIGNAL CASLNeg_nwv         : std_ulogic := 'X';
    SIGNAL CASHNeg_nwv         : std_ulogic := 'X';
    SIGNAL IO0_nwv             : UX01 := 'X';
    SIGNAL IO1_nwv             : UX01 := 'X';
    SIGNAL IO2_nwv             : UX01 := 'X';
    SIGNAL IO3_nwv             : UX01 := 'X';
    SIGNAL IO4_nwv             : UX01 := 'X';
    SIGNAL IO5_nwv             : UX01 := 'X';
    SIGNAL IO6_nwv             : UX01 := 'X';
    SIGNAL IO7_nwv             : UX01 := 'X';
    SIGNAL IO8_nwv             : UX01 := 'X';
    SIGNAL IO9_nwv             : UX01 := 'X';
    SIGNAL IO10_nwv            : UX01 := 'X';
    SIGNAL IO11_nwv            : UX01 := 'X';
    SIGNAL IO12_nwv            : UX01 := 'X';
    SIGNAL IO13_nwv            : UX01 := 'X';
    SIGNAL IO14_nwv            : UX01 := 'X';
    SIGNAL IO15_nwv            : UX01 := 'X';
    SIGNAL A0_nwv              : UX01 := 'X';
    SIGNAL A1_nwv              : UX01 := 'X';
    SIGNAL A2_nwv              : UX01 := 'X';
    SIGNAL A3_nwv              : UX01 := 'X';
    SIGNAL A4_nwv              : UX01 := 'X';
    SIGNAL A5_nwv              : UX01 := 'X';
    SIGNAL A6_nwv              : UX01 := 'X';
    SIGNAL A7_nwv              : UX01 := 'X';
    SIGNAL A8_nwv              : UX01 := 'X';
    SIGNAL A9_nwv              : UX01 := 'X';
    SIGNAL A10_nwv             : UX01 := 'X';
    SIGNAL A11_nwv             : UX01 := 'X';
    SIGNAL WENeg_nwv           : std_ulogic := 'X';
    SIGNAL RASNeg_nwv          : std_ulogic := 'X';
    SIGNAL OENeg_nwv           : std_ulogic := 'X';

    SIGNAL refreshed_in        : std_ulogic := '0';
    SIGNAL refreshed_out       : std_ulogic := '0';

BEGIN

    ----------------------------------------------------------------------------
    -- Internal Delays
    ----------------------------------------------------------------------------
    -- Artificial VITAL primitives to incorporate internal delays
    REF : VitalBuf (refreshed_out, refreshed_in, (UnitDelay, tdevice_REF));

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (IO15_ipd, IO15, tipd_IO15);
        w_2 : VitalWireDelay (IO14_ipd, IO14, tipd_IO14);
        w_3 : VitalWireDelay (IO13_ipd, IO13, tipd_IO13);
        w_4 : VitalWireDelay (IO12_ipd, IO12, tipd_IO12);
        w_5 : VitalWireDelay (IO11_ipd, IO11, tipd_IO11);
        w_6 : VitalWireDelay (IO10_ipd, IO10, tipd_IO10);
        w_7 : VitalWireDelay (IO9_ipd, IO9, tipd_IO9);
        w_8 : VitalWireDelay (IO8_ipd, IO8, tipd_IO8);
        w_9 : VitalWireDelay (IO7_ipd, IO7, tipd_IO7);
        w_10 : VitalWireDelay (IO6_ipd, IO6, tipd_IO6);
        w_11 : VitalWireDelay (IO5_ipd, IO5, tipd_IO5);
        w_12 : VitalWireDelay (IO4_ipd, IO4, tipd_IO4);
        w_13 : VitalWireDelay (IO3_ipd, IO3, tipd_IO3);
        w_14 : VitalWireDelay (IO2_ipd, IO2, tipd_IO2);
        w_15 : VitalWireDelay (IO1_ipd, IO1, tipd_IO1);
        w_16 : VitalWireDelay (IO0_ipd, IO0, tipd_IO0);
        w_17 : VitalWireDelay (A0_ipd, A0, tipd_A0);
        w_18 : VitalWireDelay (A1_ipd, A1, tipd_A1);
        w_19 : VitalWireDelay (A2_ipd, A2, tipd_A2);
        w_20 : VitalWireDelay (A3_ipd, A3, tipd_A3);
        w_21 : VitalWireDelay (A4_ipd, A4, tipd_A4);
        w_22 : VitalWireDelay (A5_ipd, A5, tipd_A5);
        w_23 : VitalWireDelay (A6_ipd, A6, tipd_A6);
        w_24 : VitalWireDelay (A7_ipd, A7, tipd_A7);
        w_25 : VitalWireDelay (A8_ipd, A8, tipd_A8);
        w_26 : VitalWireDelay (A9_ipd, A9, tipd_A9);
        w_27 : VitalWireDelay (A10_ipd, A10, tipd_A10);
        w_28 : VitalWireDelay (A11_ipd, A11, tipd_A11);
        w_30 : VitalWireDelay (CASLNeg_ipd, CASLNeg, tipd_CASLNeg);
        w_31 : VitalWireDelay (CASHNeg_ipd, CASHNeg, tipd_CASHNeg);
        w_32 : VitalWireDelay (RASNeg_ipd, RASNeg, tipd_RASNeg);
        w_33 : VitalWireDelay (WENeg_ipd, WENeg, tipd_WENeg);
        w_34 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg);

    END BLOCK;

    CASHNeg_nwv <= To_UX01(CASHNeg_ipd);
    CASLNeg_nwv <= To_UX01(CASLNeg_ipd);
    WENeg_nwv <= To_UX01(WENeg_ipd);
    RASNeg_nwv <= To_UX01(RASNeg_ipd);
    OENeg_nwv <= To_UX01(OENeg_ipd);
    IO0_nwv <= To_UX01(IO0_ipd);
    IO1_nwv <= To_UX01(IO1_ipd);
    IO2_nwv <= To_UX01(IO2_ipd);
    IO3_nwv <= To_UX01(IO3_ipd);
    IO4_nwv <= To_UX01(IO4_ipd);
    IO5_nwv <= To_UX01(IO5_ipd);
    IO6_nwv <= To_UX01(IO6_ipd);