📄 k4f641612d.vhd
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": Illegal command received" & " during refresh." SEVERITY SeverityMode; END IF; WHEN self_refresh => IF (command = ref OR command = nop)AND rass_out = '1' THEN state <= precharge, idle AFTER tdevice_TRP; Ref_Cnt := refSize; rass_in <= '0'; ELSIF (rass_out = '1') THEN ASSERT command = pre REPORT InstancePath & partID & ": Illegal command received" & " during self_refresh." SEVERITY SeverityMode; END IF; WHEN auto_refresh => IF ((command = pre) AND (rass_out = '1')) THEN null; ELSIF command=read THEN state <= bank_act; ELSIF ras_out = '1' AND command = nop THEN IF (Ref_Cnt < refSize) THEN Ref_Cnt := Ref_Cnt + 1; END IF; state <= precharge, idle AFTER tdevice_TRP; ELSIF ((command = act) AND ((WNegIn = '0') )) THEN state <= bank_act; ELSE ASSERT command = act OR command = pre REPORT InstancePath & partID & ": Illegal command received during auto_refresh." SEVERITY SeverityMode; END IF; WHEN bank_act => IF ((command = act) AND (WNegIn = '1') AND (ras_out='1') AND rcdt_out = '0')THEN state <= auto_refresh ; ELSIF (command = nop) THEN ASSERT ras_out = '1' REPORT InstancePath & partID & ": precharge command" & " does not meet tRAS time." SEVERITY SeverityMode; state <= precharge, idle AFTER tdevice_TRP; ELSIF (command = pre) THEN ASSERT rcdt_out = '0' REPORT InstancePath & partID & ": pre command received too soon after active." SEVERITY SeverityMode; MemAddr(9 downto 0):=AddressIn(9 downto 0);--latch col addr state <= wait_cmd; ELSIF (command = read) THEN ASSERT rcdt_out = '0' REPORT InstancePath & partID & ": read command received too soon after active." SEVERITY SeverityMode; MemAddr(9 downto 0):=AddressIn(9 downto 0);--latch col addr Location := to_nat(MemAddr); IF MemData1(Location) = -2 THEN DataDrive(1) := (others => 'U'); ELSIF MemData1(Location) = -1 THEN DataDrive(1) := (others => 'X'); ELSE DataDrive(1) := to_slv(MemData1(Location),8); END IF; IF MemData0(Location) = -2 THEN DataDrive(0) := (others => 'U'); ELSIF MemData0(Location) = -1 THEN DataDrive(0) := (others => 'X'); ELSE DataDrive(0) := to_slv(MemData0(Location),8); END IF; state <= read; ELSIF (command = writ) THEN ASSERT rcdt_out = '0' REPORT InstancePath & partID & ": write command" & " received too soon after active." SEVERITY SeverityMode; MemAddr(9 downto 0):=AddressIn(9 downto 0);--latch col addr Location := to_nat(MemAddr); IF Violation = '0' THEN MemData1(Location):=to_nat(DataIn(15 downto 8)); MemData0(Location):=to_nat(DataIn(7 downto 0)); ELSE MemData1(Location) := -1; MemData0(Location) := -1; END IF; state <= write; written := true; END IF; WHEN wait_cmd => IF command = read THEN Location := to_nat(MemAddr); IF MemData1(Location) = -2 THEN DataDrive(1) := (others => 'U'); ELSIF MemData1(Location) = -1 THEN DataDrive(1) := (others => 'X'); ELSE DataDrive(1) := to_slv(MemData1(Location),8); END IF; IF MemData0(Location) = -2 THEN DataDrive(0) := (others => 'U'); ELSIF MemData0(Location) = -1 THEN DataDrive(0) := (others => 'X'); ELSE DataDrive(0) := to_slv(MemData0(Location),8); END IF; state <= read; ELSIF command = writ THEN Location := to_nat(MemAddr); IF Violation = '0' THEN MemData1(Location):=to_nat(DataIn(15 downto 8)); MemData0(Location):=to_nat(DataIn(7 downto 0)); ELSE MemData1(Location) := -1; MemData0(Location) := -1; END IF; state <= write; ELSIF ((command = nop) OR (command = ref)) THEN ASSERT ras_out = '1' REPORT InstancePath & partID & ": precharge command" & " does not meet tRAS time." SEVERITY SeverityMode; state <= precharge, idle AFTER tdevice_TRP; ELSIF command = act THEN state <= bank_act; END IF; WHEN write => IF ((command = read) OR (command=writ)) THEN null; ELSIF (command = nop) THEN ASSERT ras_out = '1' REPORT InstancePath & partID & ": precharge command" & " does not meet tRAS time." SEVERITY SeverityMode; state <= precharge, idle AFTER tdevice_TRP; ELSIF (command = pre) THEN state <= wait_cmd; ELSIF (command = act) THEN state <= bank_act; END IF; WHEN read => IF (command = read) THEN null; ELSIF (command = writ) THEN ASSERT FALSE REPORT InstancePath & partID & ": Illegal command read should end before write" SEVERITY SeverityMode; state <= wait_cmd; ELSIF (command = nop) THEN state <= precharge, idle AFTER tdevice_TRP; ASSERT ras_out = '1' REPORT InstancePath & partID & ": precharge command" & " does not meet tRAS time." SEVERITY SeverityMode; ELSIF (command = pre) THEN state <= wait_cmd; ELSIF (command = act) THEN state <= bank_act; ras_in <= '1', '0' AFTER 100 us; rct_in <= '1', '0' AFTER 1 ns; rcdt_in <= '1', '0' AFTER 1 ns; END IF; END CASE; -- Check Refresh Status IF (written = true) THEN ASSERT Ref_Cnt > 0 REPORT InstancePath & partID & ": memory not refreshed (by ref_cnt)" SEVERITY SeverityMode; END IF; IF UCASNegIn = '0' AND (OENegIn = '0') THEN DataDriveOut(15 downto 8) := DataDrive(1); ELSE DataDriveOut(15 downto 8) := (OTHERS => 'Z'); END IF; IF LCASNegIn = '0' AND (OENegIn = '0') THEN DataDriveOut(7 downto 0) := DataDrive(0); ELSE DataDriveOut(7 downto 0) := (OTHERS => 'Z'); END IF; IF RASNegIn = '1' THEN ras_in <= '0'; END IF; -------------------------------------------------------------------- -- File Read Section -------------------------------------------------------------------- IF PoweredUp'EVENT and PoweredUp and (mem_file_name /= "none") THEN ind := 0; WHILE (not ENDFILE (mem_file)) LOOP READLINE (mem_file, buf); IF buf(1) = '#' THEN NEXT; ELSIF buf(1) = '@' THEN ind := h(buf(2 to 5)); ELSE MemData1(ind) := h(buf(1 to 2)); MemData0(ind) := h(buf(3 to 4)); ind := ind + 1; END IF; END LOOP; END IF; -------------------------------------------------------------------- -- Output Section -------------------------------------------------------------------- D_zd <= DataDriveOut; END PROCESS; ------------------------------------------------------------------------ -- Path Delay Process ------------------------------------------------------------------------ DataOutBlk : FOR i IN 15 DOWNTO 0 GENERATE DataOut_Delay : PROCESS (D_zd(i)) VARIABLE D_GlitchData:VitalGlitchDataArrayType(15 Downto 0); BEGIN VitalPathDelay01Z ( OutSignal => DataOut(i), OutSignalName => "Data", OutTemp => D_zd(i), Mode => OnEvent, GlitchData => D_GlitchData(i), Paths => ( 1 => (InputChangeTime => AddressIn'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A0_DQ0), PathCondition => TRUE), 2 => (InputChangeTime => OENegIn'LAST_EVENT, PathDelay => tpd_OENeg_DQ0, PathCondition => TRUE), 3 => (InputChangeTime => UCASNegIn'LAST_EVENT, PathDelay => tpd_UCASNeg_DQ0, PathCondition => TRUE), 4 => (InputChangeTime => LCASNegIn'LAST_EVENT, PathDelay => tpd_UCASNeg_DQ0, PathCondition => TRUE), 5 => (InputChangeTime => RASNegIn'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_RASNeg_DQ0), PathCondition => TRUE) ) ); END PROCESS; END GENERATE; END BLOCK;END vhdl_behavioral;
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