k4f641612d.vhd

vhdl cod for ram.For sp3e

        w_28 : VitalWireDelay (A4_ipd, A4, tipd_A4);
        w_29 : VitalWireDelay (A5_ipd, A5, tipd_A5);
        w_30 : VitalWireDelay (A6_ipd, A6, tipd_A6);
        w_31 : VitalWireDelay (A7_ipd, A7, tipd_A7);
        w_32 : VitalWireDelay (A8_ipd, A8, tipd_A8);
        w_33 : VitalWireDelay (A9_ipd, A9, tipd_A9);
        w_34 : VitalWireDelay (A10_ipd, A10, tipd_A10);
        w_35 : VitalWireDelay (A11_ipd, A11, tipd_A11);

        w_36 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg);
        w_37 : VitalWireDelay (WNeg_ipd, WNeg, tipd_WNeg);
        w_38 : VitalWireDelay (RASNeg_ipd, RASNeg, tipd_RASNeg);
        w_39 : VitalWireDelay (UCASNeg_ipd, UCASNeg, tipd_UCASNeg);
        w_40 : VitalWireDelay (LCASNeg_ipd, LCASNeg, tipd_LCASNeg);

    END BLOCK;

    OENeg_nwv   <= To_UX01(OENeg_ipd  );
    WNeg_nwv    <= To_UX01(WNeg_ipd   );
    RASNeg_nwv  <= To_UX01(RASNeg_ipd );
    UCASNeg_nwv <= To_UX01(UCASNeg_ipd);
    LCASNeg_nwv <= To_UX01(LCASNeg_ipd);

    DQ0_nwv <= To_UX01(DQ0_ipd);
    DQ1_nwv <= To_UX01(DQ1_ipd);
    DQ2_nwv <= To_UX01(DQ2_ipd);
    DQ3_nwv <= To_UX01(DQ3_ipd);
    DQ4_nwv <= To_UX01(DQ4_ipd);
    DQ5_nwv <= To_UX01(DQ5_ipd);
    DQ6_nwv <= To_UX01(DQ6_ipd);
    DQ7_nwv <= To_UX01(DQ7_ipd);
    DQ8_nwv <= To_UX01(DQ8_ipd);
    DQ9_nwv <= To_UX01(DQ9_ipd);
    DQ10_nwv <= To_UX01(DQ10_ipd);
    DQ11_nwv <= To_UX01(DQ11_ipd);
    DQ12_nwv <= To_UX01(DQ12_ipd);
    DQ13_nwv <= To_UX01(DQ13_ipd);
    DQ14_nwv <= To_UX01(DQ14_ipd);
    DQ15_nwv <= To_UX01(DQ15_ipd);
    A0_nwv <= To_UX01(A0_ipd);
    A1_nwv <= To_UX01(A1_ipd);
    A2_nwv <= To_UX01(A2_ipd);
    A3_nwv <= To_UX01(A3_ipd);
    A4_nwv <= To_UX01(A4_ipd);
    A5_nwv <= To_UX01(A5_ipd);
    A6_nwv <= To_UX01(A6_ipd);
    A7_nwv <= To_UX01(A7_ipd);
    A8_nwv <= To_UX01(A8_ipd);
    A9_nwv <= To_UX01(A9_ipd);
    A10_nwv <= To_UX01(A10_ipd);
    A11_nwv <= To_UX01(A11_ipd);

    ----------------------------------------------------------------------------
    -- Main Behavior Block
    ----------------------------------------------------------------------------
    Main : BLOCK

        PORT (
            DataIn          : IN    std_logic_vector(15 downto 0);
            DataOut         : OUT   std_logic_vector(15 downto 0);

            AddressIn       : IN    std_logic_vector(11 downto 0);
            OENegIn         : IN    std_logic := 'X';
            WNegIn          : IN    std_logic := 'X';
            RASNegIn        : IN    std_logic := 'X';
            UCASNegIn       : IN    std_logic := 'X';
            LCASNegIn       : IN    std_logic := 'X'
        );
        PORT MAP (
            DataOut(0) =>  DQ0,
            DataOut(1) =>  DQ1,
            DataOut(2) =>  DQ2,
            DataOut(3) =>  DQ3,
            DataOut(4) =>  DQ4,
            DataOut(5) =>  DQ5,
            DataOut(6) =>  DQ6,
            DataOut(7) =>  DQ7,
            DataOut(8) =>  DQ8,
            DataOut(9) =>  DQ9,
            DataOut(10) =>  DQ10,
            DataOut(11) =>  DQ11,
            DataOut(12) =>  DQ12,
            DataOut(13) =>  DQ13,
            DataOut(14) =>  DQ14,
            DataOut(15) =>  DQ15,
            DataIn(0) =>  DQ0_nwv,
            DataIn(1) =>  DQ1_nwv,
            DataIn(2) =>  DQ2_nwv,
            DataIn(3) =>  DQ3_nwv,
            DataIn(4) =>  DQ4_nwv,
            DataIn(5) =>  DQ5_nwv,
            DataIn(6) =>  DQ6_nwv,
            DataIn(7) =>  DQ7_nwv,
            DataIn(8) =>  DQ8_nwv,
            DataIn(9) =>  DQ9_nwv,
            DataIn(10) =>  DQ10_nwv,
            DataIn(11) =>  DQ11_nwv,
            DataIn(12) =>  DQ12_nwv,
            DataIn(13) =>  DQ13_nwv,
            DataIn(14) =>  DQ14_nwv,
            DataIn(15) =>  DQ15_nwv,
            AddressIn(0) => A0_nwv,
            AddressIn(1) => A1_nwv,
            AddressIn(2) => A2_nwv,
            AddressIn(3) => A3_nwv,
            AddressIn(4) => A4_nwv,
            AddressIn(5) => A5_nwv,
            AddressIn(6) => A6_nwv,
            AddressIn(7) => A7_nwv,
            AddressIn(8) => A8_nwv,
            AddressIn(9) => A9_nwv,
            AddressIn(10) => A10_nwv,
            AddressIn(11) => A11_nwv,

            OENegIn => OENeg_nwv,
            WNegIn => WNeg_nwv,
            RASNegIn => RASNeg_nwv,
            UCASNegIn => UCASNeg_nwv,
            LCASNegIn => LCASNeg_nwv
        );

        -- Type definition for state machine
        TYPE mem_state IS (pwron,
                           idle,
                           precharge,
                           test_in,
                           bank_act,
                           wait_cmd,
                           self_refresh,
                           refresh_rec,
                           auto_refresh,
                           write,
                           read
                          );

        SIGNAL state    : mem_state;

        SIGNAL D_zd     : std_logic_vector(15 DOWNTO 0);

        SIGNAL refresh      : std_logic := '0';
    BEGIN

    PoweredUp <= true after tpowerup;
    ----------------------------------------------------------------------------
    -- Main Behavior Process
    ----------------------------------------------------------------------------
        Behavior : PROCESS (DataIn, AddressIn, WNegIn, OENegIn, RASNegIn,
                            UCASNegIn, LCASNegIn, PoweredUp, state,
                            refreshed_out, ras_out, rass_out)

            -- Type definition for commands
            TYPE command_type is (
                                  nop,
                                  read,
                                  writ,
                                  act,
                                  pre,
                                  ref,
                                  test
                                 );


            -- Timing Check Variables

            VARIABLE Tviol_A0_RASNegIn         : X01 := '0';
            VARIABLE TD_A0_RASNegIn            : VitalTimingDataType;

            VARIABLE Tviol_A0_UCASNegIn        : X01 := '0';
            VARIABLE TD_A0_UCASNegIn           : VitalTimingDataType;

            VARIABLE Tviol_DQ0_UCASNegIn       : X01 := '0';
            VARIABLE TD_DQ0_UCASNegIn          : VitalTimingDataType;

            VARIABLE Tviol_WNegIn_UCASNegIn    : X01 := '0';
            VARIABLE TD_WNegIn_UCASNegIn       : VitalTimingDataType;

            VARIABLE Tviol_RASNegIn_UCASNegIn  : X01 := '0';
            VARIABLE TD_RASNegIn_UCASNegIn     : VitalTimingDataType;

            VARIABLE Tviol_UCASNegIn_RASNegIn  : X01 := '0';
            VARIABLE TD_UCASNegIn_RASNegIn     : VitalTimingDataType;

            VARIABLE Tviol_OENegIn_WNegIn      : X01 := '0';
            VARIABLE TD_OENegIn_WNegIn         : VitalTimingDataType;

            VARIABLE Pviol_WNegIn   : X01 := '0';
            VARIABLE PD_WNegIn      : VitalPeriodDataType:=VitalPeriodDataInit;

            VARIABLE Pviol_UCASNegIn: X01 := '0';
            VARIABLE PD_UCASNegIn   : VitalPeriodDataType:=VitalPeriodDataInit;

            -- Memory array declaration
            TYPE MemStore IS ARRAY (0 to depth) OF INTEGER
                             RANGE  -2 TO 255;


            TYPE OutWord IS ARRAY (1 downto 0) OF std_logic_vector(7 DOWNTO 0);


            FILE mem_file         : text IS mem_file_name;

            VARIABLE MemData0     : MemStore;
            VARIABLE MemData1     : MemStore;

            VARIABLE ind          : NATURAL := 0;
            VARIABLE buf          : line;

            VARIABLE MemAddr      : std_logic_vector(21 downto 0);
            VARIABLE Location     : NATURAL RANGE 0 TO depth := 0;

            VARIABLE command      : command_type;
            VARIABLE written      : boolean := false;
            VARIABLE chip_en      : boolean := false;


            VARIABLE Ref_Cnt      : NATURAL RANGE 0 TO refSize := 0;
            VARIABLE next_ref     : TIME;

            -- Functionality Results Variables
            VARIABLE Violation    : X01 := '0';
            VARIABLE DataDriveOut :  std_logic_vector(15 DOWNTO 0)
                                   := (OTHERS => 'Z');
            VARIABLE DataDrive    : OutWord;

        BEGIN

            --------------------------------------------------------------------
            -- Timing Check Section
            --------------------------------------------------------------------
            IF (TimingChecksOn) THEN

                VitalSetupHoldCheck (
                    TestSignal      => AddressIn,
                    TestSignalName  => "Address",
                    RefSignal       => RASNegIn,
                    RefSignalName   => "RAS#",
                    SetupHigh       => tsetup_A0_RASNeg,
                    SetupLow        => tsetup_A0_RASNeg,
                    HoldHigh        => thold_A0_RASNeg,
                    HoldLow         => thold_A0_RASNeg,
                    CheckEnabled    => chip_en,
                    RefTransition   => '\',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_A0_RASNegIn,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_A0_RASNegIn );

                VitalSetupHoldCheck (
                    TestSignal      => AddressIn,
                    TestSignalName  => "Address",
                    RefSignal       => UCASNegIn,
                    RefSignalName   => "UCAS#",
                    SetupHigh       => tsetup_A0_UCASNeg,
                    SetupLow        => tsetup_A0_UCASNeg,
                    HoldHigh        => thold_A0_UCASNeg,
                    HoldLow         => thold_A0_UCASNeg,
                    CheckEnabled    => chip_en,
                    RefTransition   => '\',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_A0_UCASNegIn,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_A0_UCASNegIn );


                VitalSetupHoldCheck (
                    TestSignal      => AddressIn,
                    TestSignalName  => "Address",
                    RefSignal       => LCASNegIn,
                    RefSignalName   => "LCAS#",
                    SetupHigh       => tsetup_A0_UCASNeg,
                    SetupLow        => tsetup_A0_UCASNeg,
                    HoldHigh        => thold_A0_UCASNeg,
                    HoldLow         => thold_A0_UCASNeg,
                    CheckEnabled    => chip_en,
                    RefTransition   => '\',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_A0_UCASNegIn,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_A0_UCASNegIn );


                VitalSetupHoldCheck (
                    TestSignal      => DataIn,
                    TestSignalName  => "DQ",
                    RefSignal       => UCASNegIn,
                    RefSignalName   => "UCAS#",
                    SetupHigh       => tsetup_DQ0_UCASNeg,
                    SetupLow        => tsetup_DQ0_UCASNeg,
                    HoldHigh        => thold_DQ0_UCASNeg,
                    HoldLow         => thold_DQ0_UCASNeg,
                    CheckEnabled    => chip_en,
                    RefTransition   => '\',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_DQ0_UCASNegIn,
                    XOn             => XOn,
                    MsgOn           => MsgOn,