k4f641612d.vhd

vhdl cod for ram.For sp3e

--------------------------------------------------------------------------------
--  File Name: k4f641612d.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2003-2008 Free Model Foundry, http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY:
--
--  version: |  author:     | mod date: | changes made:
--    V1.0    M.Marinkovic   03 APR 12   Initial release
--    V1.1    R. Munden      08 AUG 03   Corrected timing generics
--
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
--
--  Library:    DRAM
--  Technology: CMOS
--  Part:       k4f641612d
--
--  Description: 4M x 16 bit CMOS Dynamic RAM with Fast Page Mode
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
                USE STD.textio.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;
                USE FMF.conversions.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY k4f641612d IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_DQ0                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ1                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ2                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ3                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ4                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ5                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ6                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ7                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ8                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ9                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ10                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ11                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ12                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ13                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ14                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ15                : VitalDelayType01 := VitalZeroDelay01;
        tipd_A0                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A1                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A2                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A3                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A4                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A5                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A6                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A7                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A8                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A9                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A10                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A11                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_OENeg               : VitalDelayType01 := VitalZeroDelay01;
        tipd_WNeg                : VitalDelayType01 := VitalZeroDelay01;
        tipd_RASNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_UCASNeg             : VitalDelayType01 := VitalZeroDelay01;
        tipd_LCASNeg             : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_A0_DQ0               : VitalDelayType01 := UnitDelay01;
        tpd_OENeg_DQ0            : VitalDelayType01Z := UnitDelay01Z;
        tpd_UCASNeg_DQ0          : VitalDelayType01Z := UnitDelay01Z;
        tpd_RASNeg_DQ0           : VitalDelayType01 := UnitDelay01;
        -- tpw values: pulse widths
        tpw_WNeg_negedge       : VitalDelayType    := UnitDelay;
        tpw_UCASNeg_posedge    : VitalDelayType    := UnitDelay;
        -- tsetup values: setup times
        tsetup_A0_RASNeg       : VitalDelayType    := UnitDelay;
        tsetup_A0_UCASNeg      : VitalDelayType    := UnitDelay;
        tsetup_DQ0_UCASNeg     : VitalDelayType    := UnitDelay;
        tsetup_WNeg_UCASNeg  : VitalDelayType    := UnitDelay;
        -- thold values: hold times
        thold_RASNeg_UCASNeg : VitalDelayType    := UnitDelay;
        thold_UCASNeg_RASNeg : VitalDelayType    := UnitDelay;
        thold_A0_RASNeg        : VitalDelayType    := UnitDelay;
        thold_A0_UCASNeg       : VitalDelayType    := UnitDelay;
        thold_DQ0_UCASNeg      : VitalDelayType    := UnitDelay;
        thold_WNeg_UCASNeg   : VitalDelayType    := UnitDelay;
        thold_OENeg_WNeg     : VitalDelayType    := UnitDelay;
        -- tdevice values: values for internal delays
        tdevice_REF              : VitalDelayType    := 15_625 ns;
        tdevice_TRC              : VitalDelayType    := 80 ns;
        tdevice_TRCD             : VitalDelayType    := 18 ns;
        tdevice_TRP              : VitalDelayType    := 25 ns;
        tdevice_TRPS             : VitalDelayType    := 80 ns;
        tdevice_TRCAR            : VitalDelayType    := 70 ns;
        tdevice_TRASS            : VitalDelayType    := 100 us;
        tdevice_TRAS             : VitalDelayType    := 45 ns;
        --01  := (45 ns, 100_000 ns);
        tdevice_TCHR             : VitalDelayType    := 10 ns;
        -- tpowerup: Power up initialization time. Data sheets say 200 us.
        -- May be shortened during simulation debug.
        tpowerup            : TIME      := 200 us;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        SeverityMode        : SEVERITY_LEVEL := WARNING;
        -- memory file to be loaded
        mem_file_name       : STRING    := "k4f641612d.mem";
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        DQ0             : INOUT std_logic := 'U';
        DQ1             : INOUT std_logic := 'U';
        DQ2             : INOUT std_logic := 'U';
        DQ3             : INOUT std_logic := 'U';
        DQ4             : INOUT std_logic := 'U';
        DQ5             : INOUT std_logic := 'U';
        DQ6             : INOUT std_logic := 'U';
        DQ7             : INOUT std_logic := 'U';
        DQ8             : INOUT std_logic := 'U';
        DQ9             : INOUT std_logic := 'U';
        DQ10            : INOUT std_logic := 'U';
        DQ11            : INOUT std_logic := 'U';
        DQ12            : INOUT std_logic := 'U';
        DQ13            : INOUT std_logic := 'U';
        DQ14            : INOUT std_logic := 'U';
        DQ15            : INOUT std_logic := 'U';
        A0              : IN    std_logic := 'U';
        A1              : IN    std_logic := 'U';
        A2              : IN    std_logic := 'U';
        A3              : IN    std_logic := 'U';
        A4              : IN    std_logic := 'U';
        A5              : IN    std_logic := 'U';
        A6              : IN    std_logic := 'U';
        A7              : IN    std_logic := 'U';
        A8              : IN    std_logic := 'U';
        A9              : IN    std_logic := 'U';
        A10             : IN    std_logic := 'U';
        A11             : IN    std_logic := 'U';
        WNeg            : IN    std_logic := 'U';
        OENeg           : IN    std_logic := 'U';
        RASNeg          : IN    std_logic := 'U';
        UCASNeg         : IN    std_logic := 'U';
        LCASNeg         : IN    std_logic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of k4f641612d : ENTITY IS TRUE;
END k4f641612d;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of k4f641612d IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;
    CONSTANT partID            : STRING := "k4f641612d";

    CONSTANT depth             : NATURAL := 4194304; --4M( x 16b )
    CONSTANT refSize           : NATURAL := 8192;    --8K refresh
    SIGNAL PoweredUp           : boolean := false;

    SIGNAL DQ0_ipd             : std_ulogic := 'U';
    SIGNAL DQ1_ipd             : std_ulogic := 'U';
    SIGNAL DQ2_ipd             : std_ulogic := 'U';
    SIGNAL DQ3_ipd             : std_ulogic := 'U';
    SIGNAL DQ4_ipd             : std_ulogic := 'U';
    SIGNAL DQ5_ipd             : std_ulogic := 'U';
    SIGNAL DQ6_ipd             : std_ulogic := 'U';
    SIGNAL DQ7_ipd             : std_ulogic := 'U';
    SIGNAL DQ8_ipd             : std_ulogic := 'U';
    SIGNAL DQ9_ipd             : std_ulogic := 'U';
    SIGNAL DQ10_ipd            : std_ulogic := 'U';
    SIGNAL DQ11_ipd            : std_ulogic := 'U';
    SIGNAL DQ12_ipd            : std_ulogic := 'U';
    SIGNAL DQ13_ipd            : std_ulogic := 'U';
    SIGNAL DQ14_ipd            : std_ulogic := 'U';
    SIGNAL DQ15_ipd            : std_ulogic := 'U';

    SIGNAL A0_ipd              : std_ulogic := 'U';
    SIGNAL A1_ipd              : std_ulogic := 'U';
    SIGNAL A2_ipd              : std_ulogic := 'U';
    SIGNAL A3_ipd              : std_ulogic := 'U';
    SIGNAL A4_ipd              : std_ulogic := 'U';
    SIGNAL A5_ipd              : std_ulogic := 'U';
    SIGNAL A6_ipd              : std_ulogic := 'U';
    SIGNAL A7_ipd              : std_ulogic := 'U';
    SIGNAL A8_ipd              : std_ulogic := 'U';
    SIGNAL A9_ipd              : std_ulogic := 'U';
    SIGNAL A10_ipd             : std_ulogic := 'U';
    SIGNAL A11_ipd             : std_ulogic := 'U';

    SIGNAL OENeg_ipd           : std_ulogic := 'U';
    SIGNAL WNeg_ipd            : std_ulogic := 'U';
    SIGNAL RASNeg_ipd          : std_ulogic := 'U';
    SIGNAL UCASNeg_ipd         : std_ulogic := 'U';
    SIGNAL LCASNeg_ipd         : std_ulogic := 'U';

    SIGNAL DQ0_nwv             : UX01 := 'X';
    SIGNAL DQ1_nwv             : UX01 := 'X';
    SIGNAL DQ2_nwv             : UX01 := 'X';
    SIGNAL DQ3_nwv             : UX01 := 'X';
    SIGNAL DQ4_nwv             : UX01 := 'X';
    SIGNAL DQ5_nwv             : UX01 := 'X';
    SIGNAL DQ6_nwv             : UX01 := 'X';
    SIGNAL DQ7_nwv             : UX01 := 'X';
    SIGNAL DQ8_nwv             : UX01 := 'X';
    SIGNAL DQ9_nwv             : UX01 := 'X';
    SIGNAL DQ10_nwv            : UX01 := 'X';
    SIGNAL DQ11_nwv            : UX01 := 'X';
    SIGNAL DQ12_nwv            : UX01 := 'X';
    SIGNAL DQ13_nwv            : UX01 := 'X';
    SIGNAL DQ14_nwv            : UX01 := 'X';
    SIGNAL DQ15_nwv            : UX01 := 'X';
    SIGNAL A0_nwv              : UX01 := 'X';
    SIGNAL A1_nwv              : UX01 := 'X';
    SIGNAL A2_nwv              : UX01 := 'X';
    SIGNAL A3_nwv              : UX01 := 'X';
    SIGNAL A4_nwv              : UX01 := 'X';
    SIGNAL A5_nwv              : UX01 := 'X';
    SIGNAL A6_nwv              : UX01 := 'X';
    SIGNAL A7_nwv              : UX01 := 'X';
    SIGNAL A8_nwv              : UX01 := 'X';
    SIGNAL A9_nwv              : UX01 := 'X';
    SIGNAL A10_nwv             : UX01 := 'X';
    SIGNAL A11_nwv             : UX01 := 'X';

    SIGNAL OENeg_nwv           : std_logic := 'X';
    SIGNAL WNeg_nwv            : std_logic := 'X';
    SIGNAL RASNeg_nwv          : std_logic := 'X';
    SIGNAL UCASNeg_nwv         : std_logic := 'X';
    SIGNAL LCASNeg_nwv         : std_logic := 'X';
-------
    SIGNAL rct_in            : std_logic := '0';
    SIGNAL rct_out           : std_logic := '0';
    SIGNAL rcdt_in           : std_logic := '0';
    SIGNAL rcdt_out          : std_logic := '0';
    SIGNAL pre_in            : std_logic := '0';
    SIGNAL pre_out           : std_logic := '0';
    SIGNAL pres_in           : std_logic := '0';
    SIGNAL pres_out          : std_logic := '0';
    SIGNAL refreshed_in      : std_logic := '0';
    SIGNAL refreshed_out     : std_logic := '0';
    SIGNAL rcar_out          : std_logic := '0';
    SIGNAL rcar_in           : std_logic := '0';
    SIGNAL ras_in            : std_logic := '0';
    SIGNAL ras_out           : std_logic := '0';
    SIGNAL rass_in           : std_logic := '0';
    SIGNAL rass_out          : std_logic := '0';
    SIGNAL chr_in           : std_logic := '0';
    SIGNAL chr_out          : std_logic := '0';
--------
BEGIN

    ----------------------------------------------------------------------------
    -- Internal Delays
    ----------------------------------------------------------------------------
    -- Artificial VITAL primitives to incorporate internal delays
    REF   : VitalBuf (refreshed_out, refreshed_in, (UnitDelay, tdevice_REF));
    TRC   : VitalBuf (rct_out, rct_in, (tdevice_TRC, UnitDelay));
    TRCD  : VitalBuf (rcdt_out, rcdt_in, (UnitDelay, tdevice_TRCD));
    TRP   : VitalBuf (pre_out, pre_in, (tdevice_TRP, UnitDelay));
    TRPS  : VitalBuf (pres_out, pres_in, (tdevice_TRPS, UnitDelay));
    TRCAR : VitalBuf (rcar_out, rcar_in, (tdevice_TRCAR, UnitDelay));
    TRASS : VitalBuf (rass_out, rass_in, (tdevice_TRASS, UnitDelay));
    TRAS  : VitalBuf (ras_out, ras_in, (tdevice_TRAS, UnitDelay));
    TCHR  : VitalBuf (chr_out, chr_in, (UnitDelay, tdevice_TCHR));

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_5  : VitalWireDelay (DQ0_ipd, DQ0, tipd_DQ0);
        w_6  : VitalWireDelay (DQ1_ipd, DQ1, tipd_DQ1);
        w_7  : VitalWireDelay (DQ2_ipd, DQ2, tipd_DQ2);
        w_8  : VitalWireDelay (DQ3_ipd, DQ3, tipd_DQ3);
        w_9  : VitalWireDelay (DQ4_ipd, DQ4, tipd_DQ4);
        w_10 : VitalWireDelay (DQ5_ipd, DQ5, tipd_DQ5);
        w_11 : VitalWireDelay (DQ6_ipd, DQ6, tipd_DQ6);
        w_12 : VitalWireDelay (DQ7_ipd, DQ7, tipd_DQ7);
        w_13 : VitalWireDelay (DQ8_ipd, DQ8, tipd_DQ8);
        w_14 : VitalWireDelay (DQ9_ipd, DQ9, tipd_DQ9);
        w_15 : VitalWireDelay (DQ10_ipd, DQ10, tipd_DQ10);
        w_16 : VitalWireDelay (DQ11_ipd, DQ11, tipd_DQ11);
        w_17 : VitalWireDelay (DQ12_ipd, DQ12, tipd_DQ12);
        w_18 : VitalWireDelay (DQ13_ipd, DQ13, tipd_DQ13);
        w_19 : VitalWireDelay (DQ14_ipd, DQ14, tipd_DQ14);
        w_20 : VitalWireDelay (DQ15_ipd, DQ15, tipd_DQ15);

        w_24 : VitalWireDelay (A0_ipd, A0, tipd_A0);
        w_25 : VitalWireDelay (A1_ipd, A1, tipd_A1);
        w_26 : VitalWireDelay (A2_ipd, A2, tipd_A2);
        w_27 : VitalWireDelay (A3_ipd, A3, tipd_A3);