at93c46.vhd

vhdl cod for ram.For sp3e

        VARIABLE bit_cntr  : NATURAL := 0;
        VARIABLE opcode_in : std_logic_vector( 1 downto 0);
        VARIABLE addr_in   : std_logic_vector( 5 downto 0);
        VARIABLE data_in   : std_logic_vector(15 downto 0);

    BEGIN
        -----------------------------------------------------------------------
        -- Functionality Section
        -----------------------------------------------------------------------

        IF (CS = '0') AND
           (current_state /= BUSY) AND (current_state /= READY) THEN

            next_state <= NOT_SELECTED;

        ELSE

            CASE current_state IS

                WHEN NOT_SELECTED =>
                    IF rising_edge(CS) THEN
                        next_state <= SELECTED;
                    END IF;

                WHEN SELECTED     =>
                    IF rising_edge(SK) AND (DI = '1') THEN
                        next_state <= OPCODE;
                        bit_cntr := 1;
                    END IF;

                WHEN OPCODE       =>
                    IF rising_edge(SK) THEN
                        opcode_in(bit_cntr) := DI;
                        IF (bit_cntr = 0) THEN
                            CASE opcode_in(1 DOWNTO 0) IS
                                WHEN "00" =>
                                    Instruction <= NONE;
                                WHEN "01" =>
                                    Instruction <= WRITE;
                                WHEN "10" =>
                                    Instruction <= READ;
                                WHEN "11" =>
                                    Instruction <= ERASE;
                                WHEN OTHERS =>
                                    ASSERT false
                                        REPORT InstancePath & partID &
                                               ": Could not decode opcode"
                                               & " - results may be incorrect."
                                    SEVERITY Warning;

                            END CASE;
                            next_state <= ADDRESS;
                            bit_cntr := 5;
                        ELSE
                            bit_cntr := bit_cntr - 1;
                        END IF;
                    END IF;

                WHEN ADDRESS      =>
                    IF rising_edge(SK) THEN
                        addr_in(bit_cntr) := DI;
                        IF (bit_cntr = 4) AND (Instruction = NONE) THEN
                            CASE addr_in(5 DOWNTO 4) IS
                                WHEN "00" =>
                                    Instruction <= EWDS;
                                WHEN "01" =>
                                    Instruction <= WRAL;
                                WHEN "10" =>
                                    Instruction <= ERAL;
                                WHEN "11" =>
                                    Instruction <= EWEN;
                                WHEN OTHERS =>
                                    ASSERT false
                                        REPORT InstancePath & partID &
                                               ": Could not decode opcode"
                                               & " - results may be incorrect."
                                    SEVERITY Warning;
                            END CASE;
                            bit_cntr := bit_cntr - 1;
                        ELSIF (bit_cntr = 0) THEN
                            Addr <= to_nat(addr_in);
                            CASE Instruction IS
                                WHEN READ =>
                                    next_state <= READ;
                                    bit_cntr := 16;
                                WHEN EWEN =>
                                    write_enabled := true;
                                    next_state <= SELECTED;
                                WHEN EWDS =>
                                    write_enabled := false;
                                    next_state <= SELECTED;
                                WHEN ERASE | ERAL =>
                                    IF (write_enabled = true) THEN
                                        next_state <= BUSY;
                                        IF (TimingModel(1 to 2) /= "FM") THEN
                                            WP_in <= '1', '0' AFTER 1 ns;
                                        END IF;
                                    ELSE
                                        next_state <= SELECTED;
                                    END IF;
                                WHEN WRITE | WRAL =>
                                    next_state <= DATA;
                                    bit_cntr := 15;
                                WHEN OTHERS =>
                                    ASSERT false
                                        REPORT InstancePath & partID &
                                               ": Could not decode opcode"
                                               & " - results may be incorrect."
                                    SEVERITY Warning;
                            END CASE;
                        ELSE
                            bit_cntr := bit_cntr - 1;
                        END IF;
                    END IF;

                WHEN DATA         =>
                    IF rising_edge(SK) THEN
                        data_in(bit_cntr) := DI;
                        IF (bit_cntr = 0) THEN
                            DataWord <= to_nat(data_in);
                            IF (write_enabled = true) THEN
                                next_state <= BUSY;
                                IF (TimingModel(1 to 2) /= "FM") THEN
                                    WP_in <= '1', '0' AFTER 1 ns;
                                END IF;
                            ELSE
                                next_state <= SELECTED;
                            END IF;
                        ELSE
                            bit_cntr := bit_cntr - 1;
                        END IF;
                    END IF;

                WHEN READ         =>
                    IF rising_edge(SK) THEN
                        IF (bit_cntr = 0) THEN
                            next_state <= SELECTED;
                        ELSE
                            bit_cntr := bit_cntr - 1;
                        END IF;
                    END IF;

                WHEN BUSY         =>
                    IF (TimingModel(1 to 2) = "FM") AND
                       falling_edge(CS) AND (WP_out = '0') THEN
                        WP_in <= '1', '0' AFTER 1 ns;
                    END IF;
                    IF falling_edge(WP_out) THEN
                        write_event <= '1', '0' AFTER 1 ns;
                        IF (CS = '1') THEN
                            next_state <= READY;
                        ELSE
                            next_state <= NOT_SELECTED;
                        END IF;
                    END IF;

                WHEN READY        =>
                    IF (CS = '0') THEN
                        next_state <= NOT_SELECTED;
                    ELSIF rising_edge(SK) AND (DI = '1') THEN
                        next_state <= OPCODE;
                        bit_cntr := 1;
                    END IF;

            END CASE;

        END IF;

    END PROCESS StateGen;

    ---------------------------------------------------------------------------
    --FSM Output generation and general funcionality
    ---------------------------------------------------------------------------
    Functional : PROCESS(current_state, SK, CS, write_event)

        VARIABLE read_cntr   : INTEGER := 0;
        VARIABLE data_out    : std_logic_vector(15 downto 0);

    BEGIN
        -----------------------------------------------------------------------
        -- Functionality Section
        -----------------------------------------------------------------------

        CASE current_state IS

            WHEN READ   =>
                IF (current_state'EVENT) THEN
                    DO_zd <= '0';
                    data_out := to_slv(Mem(Addr), 16);
                    read_cntr := 15;
                ELSIF rising_edge(SK) AND (read_cntr > -1) THEN
                    DO_zd <= data_out(read_cntr);
                    read_cntr := read_cntr - 1;
                END IF;

            WHEN BUSY   =>
                IF rising_edge(CS) THEN
                    DO_zd <= '0';
                ELSIF (CS = '0') THEN
                    DO_zd <= 'Z';
                END IF;
                IF rising_edge(write_event) THEN
                    CASE Instruction IS
                        WHEN ERASE =>
                            Mem(Addr) := MaxData;
                        WHEN ERAL =>
                            FOR I IN Mem'RANGE LOOP
                                Mem(I) := MaxData;
                            END LOOP;
                        WHEN WRITE =>
                            Mem(Addr) := DataWord;
                        WHEN WRAL =>
                            FOR I IN Mem'RANGE LOOP
                                Mem(I) := DataWord;
                            END LOOP;
                        WHEN OTHERS =>
                            ASSERT false
                                REPORT InstancePath & partID &
                                       ": Could not decode opcode"
                                       & " - results may be incorrect."
                            SEVERITY Warning;
                    END CASE;
                END IF;

            WHEN READY  =>
                IF rising_edge(SK) AND (DI = '1') THEN
                    DO_zd <= 'Z';
                ELSE
                    DO_zd <= '1';
                END IF;

            WHEN OTHERS =>
                DO_zd <= 'Z';

        END CASE;

    END PROCESS Functional;

    ---------------------------------------------------------------------------
    ---- File Read Section - Preload Control
    ---------------------------------------------------------------------------
    MemPreload : PROCESS

        -- text file input variables
        FILE mem_file        : text  is  mem_file_name;
        VARIABLE ind         : NATURAL := 0;
        VARIABLE buf         : line;

    BEGIN
    ---------------------------------------------------------------------------
    -- at93c46 memory preload file format-- -----------------------------------
    ---------------------------------------------------------------------------
    --   /    - comment
    --   @aa  - <aa> stands for address
    --   dddd - <dddd> is word to be written at Mem(aa++)
    --                (aa is incremented at every load)
    --   only first 1-4 columns are loaded. NO empty lines !!!!!!!!!!!!!!!!
    ---------------------------------------------------------------------------

        -- memory preload
        IF (mem_file_name /= "none" AND UserPreload) THEN
            ind := 0;
            Mem := (OTHERS => MaxData);
            WHILE (not ENDFILE (mem_file)) LOOP
                READLINE (mem_file, buf);
                IF buf(1) = '/' THEN
                    NEXT;
                ELSIF buf(1) = '@' THEN
                    ind := h(buf(2 to 3)); --address
                ELSE
                    IF ind > AddrRANGE THEN
                        ASSERT false
                            REPORT "Given preload address is out of " &
                                   "memory address range"
                            SEVERITY warning;
                    ELSE
                        Mem(ind) := h(buf(1 to 4));
                        ind := ind + 1;
                    END IF;
                END IF;
            END LOOP;
        END IF;

        WAIT;
    END PROCESS MemPreload;

    DO_OUT: PROCESS(DO_zd)

        VARIABLE DO_GlitchData : VitalGlitchDataType;
    BEGIN
        VitalPathDelay01Z (
            OutSignal       => DO,
            OutSignalName   => "DO",
            OutTemp         => DO_zd,
            GlitchData      => DO_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime => SK_ipd'LAST_EVENT,
                      PathDelay       => VitalExtendtofillDelay(tpd_SK_DO),
                      PathCondition   => true),
                1 => (InputChangeTime => CS_ipd'LAST_EVENT,
                      PathDelay       => tpd_CS_DO,
                      PathCondition   => true)
            )
        );
    END PROCESS DO_OUT;

    END BLOCK behavior;
END vhdl_behavioral;