at93c46.vhd

vhdl cod for ram.For sp3e

-------------------------------------------------------------------------------
--  File Name: at93c46.vhd
-------------------------------------------------------------------------------
-- Copyright (C) 2005 Free Model Foundry; http://www.FreeModelFoundry.com
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License version 2 as
-- published by the Free Software Foundation.
--
-- MODIFICATION HISTORY:
--
-- version: |  author:         | mod date: | changes made:
--  V1.0       Dj.Tanasijevic    05 SEP 14   initial release
--
-------------------------------------------------------------------------------
--  PART DESCRIPTION:
--
--  Library:    RAM
--  Technology: CMOS
--  Part:       AT93C46
--
--  Description: 1024-Bit (64x16) 3-Wire Serial EEPROM
--
-------------------------------------------------------------------------------
LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
                USE STD.textio.ALL;

LIBRARY FMF;    USE FMF.gen_utils.ALL;
                USE FMF.conversions.ALL;

-------------------------------------------------------------------------------
-- ENTITY DECLARATION
-------------------------------------------------------------------------------
ENTITY at93c46 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_CS              : VitalDelayType01 := VitalZeroDelay01;
        tipd_SK              : VitalDelayType01 := VitalZeroDelay01;
        tipd_DI              : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_SK_DO            : VitalDelayType01  := UnitDelay01;  --tPD
        tpd_CS_DO            : VitalDelayType01Z := UnitDelay01Z; --tSV, tDF
        --tsetup values
        tsetup_CS_SK         : VitalDelayType := UnitDelay;       --tCSS
        tsetup_DI_SK         : VitalDelayType := UnitDelay;       --tDIS
        --thold values
        thold_CS_SK          : VitalDelayType := UnitDelay;       --tCSH
        thold_DI_SK          : VitalDelayType := UnitDelay;       --tDIH
        --tpw values: pulse width
        tpw_SK_posedge       : VitalDelayType := UnitDelay;       --tSKH
        tpw_SK_negedge       : VitalDelayType := UnitDelay;       --tCSKL
        tpw_CS_negedge       : VitalDelayType := UnitDelay;       --tCS
        -- tperiod min (calculated as 1/max_freq)
        tperiod_SK           : VitalDelayType := UnitDelay;       --1/fSK
        -- tdevice values: values for internal delays
            -- Write Cycle Operation
        tdevice_WP           : VitalDelayType    := 1 ms;         --tWP
        -- generic control parameters
        InstancePath      : STRING    := DefaultInstancePath;
        TimingChecksOn    : BOOLEAN   := DefaultTimingChecks;
        MsgOn             : BOOLEAN   := DefaultMsgOn;
        XOn               : BOOLEAN   := DefaultXon;
        -- memory file to be loaded
        mem_file_name     : STRING    := "at93c46.mem";
        UserPreload       : BOOLEAN   := FALSE; --TRUE;
        -- For FMF SDF technology file usage
        TimingModel       : STRING    := DefaultTimingModel
    );
    PORT (
        CS            : IN    std_ulogic := 'U'; -- chip select input
        SK            : IN    std_ulogic := 'U'; -- serial data clock input
        DI            : IN    std_ulogic := 'U'; -- serial data input
        DO            : OUT   std_ulogic := 'U'  -- serial data output
    );
    ATTRIBUTE VITAL_LEVEL0 of at93c46 : ENTITY IS TRUE;
END at93c46;

-------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
-------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of at93c46 IS
    ATTRIBUTE VITAL_LEVEL0 OF vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT PartID        : STRING  := "at93c46";
    CONSTANT MaxData       : NATURAL := 16#FFFF#;
    CONSTANT AddrRANGE     : NATURAL := 16#3F#;

-- interconnect path delay signals
    SIGNAL CS_ipd          : std_ulogic := 'U';
    SIGNAL SK_ipd          : std_ulogic := 'U';
    SIGNAL DI_ipd          : std_ulogic := 'U';

    ---  internal delays
    SIGNAL WP_in           : std_ulogic := '0';
    SIGNAL WP_out          : std_ulogic := '0';

BEGIN
    ---------------------------------------------------------------------------
    -- Internal Delays
    ---------------------------------------------------------------------------
    -- Artificial VITAL primitives to incorporate internal delays
    WP : VitalBuf(WP_out, WP_in, (UnitDelay, tdevice_WP));

    ---------------------------------------------------------------------------
    -- Wire Delays
    ---------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (CS_ipd, CS, tipd_CS);
        w_2 : VitalWireDelay (SK_ipd, SK, tipd_SK);
        w_3 : VitalWireDelay (DI_ipd, DI, tipd_DI);

    END BLOCK;

    ---------------------------------------------------------------------------
    -- Main Behavior Block
    ---------------------------------------------------------------------------
    Behavior : BLOCK
        PORT (
            CS        : IN  std_ulogic    :=  'U';
            SK        : IN  std_ulogic    :=  'U';
            DI        : IN  std_ulogic    :=  'U';
            DO        : OUT std_ulogic    :=  'U'
            );
        PORT MAP (
            CS        => CS_ipd,
            SK        => SK_ipd,
            DI        => DI,
            DO        => DO
            );

        -- State Machine : State_Type
        TYPE state_type IS (NOT_SELECTED,
                            SELECTED,
                            OPCODE,
                            ADDRESS,
                            DATA,
                            READ,
                            BUSY,
                            READY
                            );

        -- Instruction type
        TYPE instruction_type IS (NONE,
                                  READ,
                                  EWEN,
                                  ERASE,
                                  WRITE,
                                  ERAL,
                                  WRAL,
                                  EWDS);

        -- EEPROM Memory Array
        TYPE MemArray IS ARRAY (0 TO AddrRANGE) OF INTEGER RANGE -1 TO MaxData;
        SHARED VARIABLE Mem     : MemArray := ( OTHERS => MaxData);

        -- states
        SIGNAL current_state    : state_type;  --
        SIGNAL next_state       : state_type;  --

       -- zero delay signal
        SIGNAL DO_zd            : std_logic := 'Z';

        -- Write enable indication
        SHARED VARIABLE write_enabled : boolean := false ;

        -- Write/Erase internal operation finished indication
        SIGNAL write_event      : std_logic  := '0';

        SIGNAL Addr             : NATURAL RANGE 0 TO AddrRANGE := 0;
        SIGNAL DataWord         : NATURAL RANGE 0 TO MaxData   := 0;
        SIGNAL Instruction      : instruction_type := NONE;

        -- timing check violation
        SIGNAL Viol             : X01 := '0';

    BEGIN
    ---------------------------------------------------------------------------
    -- VITAL Timing Checks Procedures
    ---------------------------------------------------------------------------
    VITALTimingCheck: PROCESS(CS_ipd, SK_ipd, DI_ipd)
         -- Timing Check Variables
        VARIABLE Tviol_CS_SK_s   : X01 := '0';
        VARIABLE TD_CS_SK_s      : VitalTimingDataType;

        VARIABLE Tviol_CS_SK_h   : X01 := '0';
        VARIABLE TD_CS_SK_h      : VitalTimingDataType;

        VARIABLE Tviol_DI_SK     : X01 := '0';
        VARIABLE TD_DI_SK        : VitalTimingDataType;

        VARIABLE Pviol_SK        : X01 := '0';
        VARIABLE PD_SK           : VitalPeriodDataType := VitalPeriodDataInit;

        VARIABLE Pviol_CS        : X01 := '0';
        VARIABLE PD_CS           : VitalPeriodDataType := VitalPeriodDataInit;

        VARIABLE Violation       : X01 := '0';

    BEGIN
        -----------------------------------------------------------------------
        -- Timing Check Section
        -----------------------------------------------------------------------
        IF (TimingChecksOn) THEN

            -- Setup Check between CS and SK
            VitalSetupHoldCheck (
                TestSignal      => CS_ipd,
                TestSignalName  => "CS",
                RefSignal       => SK_ipd,
                RefSignalName   => "SK",
                SetupHigh       => tsetup_CS_SK,
                SetupLow        => tsetup_CS_SK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_CS_SK_s,
                Violation       => Tviol_CS_SK_s
            );

            -- Hold Check between CS and SK
            VitalSetupHoldCheck (
                TestSignal      => CS_ipd,
                TestSignalName  => "CS",
                RefSignal       => SK_ipd,
                RefSignalName   => "SK",
                HoldHigh        => thold_CS_SK,
                HoldLow         => thold_CS_SK,
                CheckEnabled    => true,
                RefTransition   => '\',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_CS_SK_h,
                Violation       => Tviol_CS_SK_h
            );

            -- Setup/Hold Check between DI and SK
            VitalSetupHoldCheck (
                TestSignal      => DI_ipd,
                TestSignalName  => "DI",
                RefSignal       => SK_ipd,
                RefSignalName   => "SK",
                SetupHigh       => tsetup_DI_SK,
                SetupLow        => tsetup_DI_SK,
                HoldHigh        => thold_DI_SK,
                HoldLow         => thold_DI_SK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & PartID,
                TimingData      => TD_DI_SK,
                Violation       => Tviol_DI_SK
            );

            -- Period Check SK
            VitalPeriodPulseCheck (
                TestSignal      =>  SK_ipd,
                TestSignalName  =>  "SK",
                PulseWidthHigh  =>  tpw_SK_posedge,
                PulseWidthLow   =>  tpw_SK_posedge,
                Period          =>  tperiod_SK,
                PeriodData      =>  PD_SK,
                XOn             =>  XOn,
                MsgOn           =>  MsgOn,
                Violation       =>  Pviol_SK,
                HeaderMsg       =>  InstancePath & PartID,
                CheckEnabled    =>  true );

            -- Period Check Reset#
            VitalPeriodPulseCheck (
                TestSignal      =>  CS_ipd,
                TestSignalName  =>  "CS",
                PulseWidthLow   =>  tpw_CS_negedge,
                PeriodData      =>  PD_CS,
                XOn             =>  XOn,
                MsgOn           =>  MsgOn,
                Violation       =>  Pviol_CS,
                HeaderMsg       =>  InstancePath & PartID,
                CheckEnabled    =>  true );

            Violation := Tviol_CS_SK_s OR
	                 Tviol_CS_SK_h OR
                         Tviol_DI_SK   OR
                         Pviol_SK      OR
                         Pviol_CS;

            Viol <= Violation;

            ASSERT Violation = '0'
                REPORT InstancePath & partID & ": simulation may be" &
                        " inaccurate due to timing violations"
                SEVERITY WARNING;

        END IF;
    END PROCESS VITALTimingCheck;

    ---------------------------------------------------------------------------
    -- sequential process for FSM state transition
    ---------------------------------------------------------------------------
    StateTransition : PROCESS(next_state)

    BEGIN
        current_state <= next_state;
    END PROCESS StateTransition;

    ---------------------------------------------------------------------------
    -- Main Behavior Process
    -- combinational process for next state generation
    ---------------------------------------------------------------------------
    StateGen: PROCESS(CS, SK, WP_out)