mt48lc8m8.vhd

vhdl cod for ram.For sp3e

                    IF cur_bank = bank THEN

                        FixColumnAddress(bank);

                        ReadFromMem(bank);

                        Burst_Cnt(bank) := 1;
                        IF (AddressIn(10) = '0') THEN
                            statebank(bank) <= read;
                        ELSIF (AddressIn(10) = '1') THEN
                            statebank(bank) <= read_auto_pre;
                        END IF;
                    ELSE
                        statebank(bank) <= bank_act;
                    END IF;
                ELSIF (command = writ) THEN
                    IF cur_bank = bank THEN
                        IF (Burst_Cnt(bank) = Burst_Length) THEN
                            statebank(bank) <= bank_act;
                            Burst_Cnt(bank) := 0;
                            ras_in(bank) <= '1';
                            Burst_Inc(bank) := 0;
                        ELSE

                            FixColumnAddress(bank);
                            WriteToMem(bank);

                            ASSERT ((AddressIn(10) = '0') OR
                                    (AddressIn(10) = '1'))
                                REPORT InstancePath & partID & BankString &
                                    ": AddressIn(10) = X"
                                & " during write command. Next state unknown."
                                SEVERITY SeverityMode;
                            IF (AddressIn(10) = '0') THEN
                                statebank(bank) <= write;
                            ELSIF (AddressIn(10) = '1') THEN
                                statebank(bank) <= write_auto_pre;
                            END IF;
                            Burst_Cnt(bank) := 1;
                            written := true;
                        END IF;
                    ELSE
                        statebank(bank)<=bank_act;
                    END IF;
                ELSIF (command = pre) AND ((cur_bank = bank) OR
                       (AddressIn(10) = '1')) THEN
                    statebank(bank) <= precharge, idle AFTER tdevice_TRP;
                    ASSERT ras_out(bank) = '1'
                        REPORT InstancePath & partID & BankString &
                           ": precharge command"
                               & " does not meet tRAS time."
                        SEVERITY SeverityMode;
                ELSIF (command = nop) OR (cur_bank /= bank) THEN
                    IF (Burst_Cnt(bank) = Burst_Length) THEN
                        statebank(bank) <= bank_act;
                        Burst_Cnt(bank) := 0;
                        ras_in(bank) <= '1';
                        Burst_Inc(bank) := 0;
                    ELSE
                        statebank(bank) <= read;

                        BurstCtrl(bank);

                        ReadFromMem(bank);

                    END IF;
                ELSIF cur_bank = bank THEN
                    ASSERT false
                        REPORT InstancePath & partID & BankString &
                               ": Illegal command"
                               & " received in read state."
                        SEVERITY SeverityMode;
                END IF;

            WHEN write_auto_pre =>
                IF (command = nop) OR (cur_bank /= bank) THEN
                    IF (Burst_Cnt(bank) = Burst_Length OR WB = single) THEN
                        statebank(bank) <= precharge, idle AFTER tdevice_TRP;
                        Burst_Cnt(bank) := 0;
                        ras_in(bank) <= '1';
                        Burst_Inc(bank) := 0;
                    ELSE
                        statebank(bank)<=write_auto_pre;

                        BurstCtrl(bank);
                        WriteToMem(bank);

                    END IF;
               ELSE
                    ASSERT false
                        REPORT InstancePath & partID & BankString &
                               ": Illegal command"
                               & " received in write state."
                        SEVERITY SeverityMode;
                END IF;

            WHEN read_auto_pre =>
                IF (command = nop) OR (cur_bank /= bank) THEN
                    IF (Burst_Cnt(bank) = Burst_Length) THEN
                        statebank(bank) <= precharge, idle AFTER tdevice_TRP;
                        Burst_Cnt(bank) := 0;
                        ras_in(bank) <= '1';
                        Burst_Inc(bank) := 0;
                    ELSE
                        statebank(bank) <=read_auto_pre;

                        BurstCtrl(bank);
                        ReadFromMem(bank);

                    END IF;
                ELSIF (command = read) AND (cur_bank /= bank) THEN
                    statebank(bank) <= precharge, idle AFTER tdevice_TRP;
                ELSE
                    ASSERT false
                        REPORT InstancePath & partID & BankString &
                               ": Illegal command"
                               & " received in read state."
                        SEVERITY SeverityMode;
                END IF;

            WHEN others => null;
        END CASE;
        END LOOP banks;

    -- Check Refresh Status
        IF (written = true) THEN
            ASSERT Ref_Cnt > 0
                REPORT InstancePath & partID &
                       ": memory not refreshed (by ref_cnt)"
                SEVERITY SeverityMode;
        END IF;

    END IF;

    --------------------------------------------------------------------
    -- Output Section
    --------------------------------------------------------------------
    IF rising_edge(CLKIn) THEN
        DQM_reg2 := DQM_reg1;
        DQM_reg1 := DQMIn;
        IF (CAS_Lat = 2) THEN
            DataDriveOut := DataDrive2;
        ELSE
            DataDriveOut := DataDrive3;
        END IF;

        IF DQM_reg2 = '1' THEN
            D_zd <= (OTHERS => 'Z');
        ELSE
            D_zd <= DataDriveOut;
        END IF;
        IF  CKEreg = '1' THEN
            DataDrive3 := DataDrive2;
            DataDrive2 := DataDrive1;
            DataDrive1 := DataDrive;
        END IF;
    END IF;


   -- The Powering-down State Machine
    IF (rising_edge(CLKIn) AND CKEreg = '1' AND CKEIn = '0') THEN

        ASSERT (not(Is_X(CSNegIn)))
            REPORT InstancePath & partID & ": Unusable value for CSNeg"
            SEVERITY SeverityMode;

        IF (CSNegIn = '1') THEN
            command := nop;
        END IF;

        CASE statebank(cur_bank) IS
            WHEN idle =>
                IF (command = nop) THEN
                    statebank <= pwrdwn & pwrdwn & pwrdwn & pwrdwn;
                ELSIF (command = ref) THEN
                    statebank <= self_refresh & self_refresh & self_refresh
                             & self_refresh;
                END IF;
            WHEN write =>
                    statebank(cur_bank) <= write_suspend;
            WHEN read =>
                    statebank(cur_bank) <= read_suspend;
            WHEN bank_act =>
                IF (command = writ) THEN
                    statebank(cur_bank) <= write_suspend;
                ELSIF (command = read) THEN
                    statebank(cur_bank) <= read_suspend;
                ELSE
                    statebank(cur_bank) <= bank_act_pwrdwn;
                END IF;
            WHEN others => null;
        END CASE;

    END IF;

    -- The Powering-up State Machine
    IF (rising_edge(CLKIn) AND CKEreg = '0' AND CKEIn = '1') THEN

        ASSERT (not(Is_X(CSNegIn)))
            REPORT InstancePath & partID & ": Unusable value for CSNeg"
            SEVERITY SeverityMode;

        IF (CSNegIn = '1') THEN
            command := nop;
        END IF;

        CASE statebank(cur_bank) IS
            WHEN write_suspend =>
                statebank(cur_bank) <= write;
            WHEN read_suspend =>
                statebank(cur_bank) <= read;
            WHEN self_refresh =>
                statebank <= idle & idle & idle & idle after tdevice_TRP;
                Ref_Cnt := 8192;
                ASSERT command = nop
                    REPORT InstancePath & partID & ": Illegal command received"
                           & " during self_refresh."
                    SEVERITY SeverityMode;
            WHEN pwrdwn =>
               statebank <= idle & idle & idle & idle;
            WHEN bank_act_pwrdwn =>
                statebank(cur_bank) <= bank_act;
            WHEN others => null;
        END CASE;

    END IF;

    --------------------------------------------------------------------
    -- File Read Section
    --------------------------------------------------------------------
    -- mt48lc8m8 memory preload file format
    --------------------------------------------------------------------
    --  /       - comment
    --  @baaaaaa  - <b> stands for bank, i
    --            <aaaaaa> stands for address within bank
    --  dd      - <dd> is byte to be written at Mem(*)(aaaaaa++)
    --            (aaaaaa is incremented at every load)
    --  only first 1-8 columns are loaded. NO empty lines !
    --------------------------------------------------------------------
    IF PoweredUp'EVENT and PoweredUp and (mem_file_name /= "none") THEN
        ind := 0;
        file_bank:=0;
        WHILE (not ENDFILE (mem_file)) LOOP
           READLINE (mem_file, buf);
            IF buf(1) = '/' THEN
                NEXT;
            ELSIF buf(1) = '@' THEN
                file_bank := h(buf(2 to 2));
                ind := h(buf(3 to 8));
            ELSE
                -- both bytes have the same value
                MemData(file_bank)(ind) := h(buf(1 to 2));
                ind := ind + 1;
            END IF;
        END LOOP;
    END IF;

END PROCESS;

------------------------------------------------------------------------
-- Path Delay Process
------------------------------------------------------------------------
DataOutBlk : FOR i IN HiDataBit DOWNTO 0 GENERATE
    DataOut_Delay : PROCESS (D_zd(i))
        VARIABLE D_GlitchData:VitalGlitchDataArrayType(HiDataBit Downto 0);
    BEGIN
        VitalPathDelay01Z (
            OutSignal       => DataOut(i),
            OutSignalName   => "Data",
            OutTemp         => D_zd(i),
            Mode            => OnEvent,
            GlitchData      => D_GlitchData(i),
            Paths           => (
                0 => (InputChangeTime => CLKin'LAST_EVENT,
                      PathDelay => tpd_CLK_DQ0,
                      PathCondition   => CAS_Lat=2 ),
                1 => (InputChangeTime => CLKin'LAST_EVENT,
                      PathDelay => tpd_CLK_DQ1,
                      PathCondition   => NOT (CAS_Lat=2) )
           )
        );

    END PROCESS;
END GENERATE;

END BLOCK;

END vhdl_behavioral;