📄 mt48lc8m8.vhd
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-------------------------------------------------------------------- IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => BAIn, TestSignalName => "BA", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_A0_CLK, SetupLow => tsetup_A0_CLK, HoldHigh => thold_A0_CLK, HoldLow => thold_A0_CLK, CheckEnabled => chip_en, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_BA_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BA_CLK ); VitalSetupHoldCheck ( TestSignal => DataIn, TestSignalName => "Data", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_DQ0_CLK, SetupLow => tsetup_DQ0_CLK, HoldHigh => thold_DQ0_CLK, HoldLow => thold_DQ0_CLK, CheckEnabled => chip_en AND NOT(DataIn(0)='X' AND D_zd(0)='Z'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_D0_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D0_CLK ); VitalSetupHoldCheck ( TestSignal => CKEIn, TestSignalName => "CKE", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_CKE_CLK, SetupLow => tsetup_CKE_CLK, HoldHigh => thold_CKE_CLK, HoldLow => thold_CKE_CLK, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CKE_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CKE_CLK ); VitalSetupHoldCheck ( TestSignal => AddressIn, TestSignalName => "Address", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_A0_CLK, SetupLow => tsetup_A0_CLK, HoldHigh => thold_A0_CLK, HoldLow => thold_A0_CLK, CheckEnabled => chip_en, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_Address_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_Address_CLK ); VitalSetupHoldCheck ( TestSignal => WENegIn, TestSignalName => "WENeg", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_CSNeg_CLK, SetupLow => tsetup_CSNeg_CLK, HoldHigh => thold_CSNeg_CLK, HoldLow => thold_CSNeg_CLK, CheckEnabled => chip_en, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_WENeg_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENeg_CLK ); VitalSetupHoldCheck ( TestSignal => RASNegIn, TestSignalName => "RASNeg", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_CSNeg_CLK, SetupLow => tsetup_CSNeg_CLK, HoldHigh => thold_CSNeg_CLK, HoldLow => thold_CSNeg_CLK, CheckEnabled => chip_en, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RASNeg_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RASNeg_CLK ); VitalSetupHoldCheck ( TestSignal => CSNegIn, TestSignalName => "CSNeg", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_CSNeg_CLK, SetupLow => tsetup_CSNeg_CLK, HoldHigh => thold_CSNeg_CLK, HoldLow => thold_CSNeg_CLK, CheckEnabled => chip_en, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CSNeg_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CSNeg_CLK ); VitalSetupHoldCheck ( TestSignal => CASNegIn, TestSignalName => "CASNeg", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_CSNeg_CLK, SetupLow => tsetup_CSNeg_CLK, HoldHigh => thold_CSNeg_CLK, HoldLow => thold_CSNeg_CLK, CheckEnabled => chip_en, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CASNeg_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CASNeg_CLK ); VitalSetupHoldCheck ( TestSignal => DQMIn, TestSignalName => "DQM", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_CSNeg_CLK, SetupLow => tsetup_CSNeg_CLK, HoldHigh => thold_CSNeg_CLK, HoldLow => thold_CSNeg_CLK, CheckEnabled => chip_en, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQM_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DQM_CLK ); VitalPeriodPulseCheck ( TestSignal => CLKIn, TestSignalName => "CLK", Period => tperiod_CLK, PulseWidthLow => tpw_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PeriodData => PD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLK, HeaderMsg => InstancePath & PartID, CheckEnabled => CAS_Lat=2 ); VitalPeriodPulseCheck ( TestSignal => CLKIn, TestSignalName => "CLK", Period => tperiod_CLK_CAS3, PulseWidthLow => tpw_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PeriodData => PD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLK, HeaderMsg => InstancePath & PartID, CheckEnabled => CAS_Lat/=2 ); Violation := Pviol_CLK OR Tviol_BA_CLK OR Tviol_DQM_CLK OR Tviol_CKE_CLK OR Tviol_Address_CLK OR Tviol_WENeg_CLK OR Tviol_RASNeg_CLK OR Tviol_CSNeg_CLK OR Tviol_CASNeg_CLK; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY SeverityMode; END IF; -- Timing Check Section -------------------------------------------------------------------- -- Functional Section -------------------------------------------------------------------- IF (rising_edge(CLKIn)) THEN CKEreg <= CKE_nwv; IF (NOW > Next_Ref AND PoweredUp AND Ref_Cnt > 0) THEN Ref_Cnt := Ref_Cnt - 1; Next_Ref := NOW + tdevice_REF; END IF; IF CKEreg = '1' THEN IF CSNegIn = '0' THEN chip_en := true; ELSE chip_en := false; END IF; END IF; END IF; IF (rising_edge(CLKIn) AND CKEreg = '1' AND to_X01(CSNegIn) = '1') THEN command := nop; ELSIF (rising_edge(CLKIn) AND CKEreg = '1' AND to_X01(CSNegIn) = '0') THEN ASSERT (not(Is_X(WENegIn))) REPORT InstancePath & partID & ": Unusable value for WENeg" SEVERITY SeverityMode; ASSERT (not(Is_X(RASNegIn))) REPORT InstancePath & partID & ": Unusable value for RASNeg" SEVERITY SeverityMode; ASSERT (not(Is_X(CASNegIn))) REPORT InstancePath & partID & ": Unusable value for CASNeg" SEVERITY SeverityMode; -- Command Decode IF ((RASNegIn = '1') AND (CASNegIn = '1') AND (WENegIn = '1')) THEN command := nop; ELSIF ((RASNegIn = '0') AND (CASNegIn = '1') AND (WENegIn = '1')) THEN command := act; ELSIF ((RASNegIn = '1') AND (CASNegIn = '0') AND (WENegIn = '1')) THEN command := read; ELSIF ((RASNegIn = '1') AND (CASNegIn = '0') AND (WENegIn = '0')) THEN command := writ; ELSIF ((RASNegIn = '1') AND (CASNegIn = '1') AND (WENegIn = '0')) THEN command := bst; ELSIF ((RASNegIn = '0') AND (CASNegIn = '1') AND (WENegIn = '0')) THEN command := pre; ELSIF ((RASNegIn = '0') AND (CASNegIn = '0') AND (WENegIn = '1')) THEN command := ref; ELSIF ((RASNegIn = '0') AND (CASNegIn = '0') AND (WENegIn = '0')) THEN command := mrs; END IF; -- PowerUp Check IF (NOT(PoweredUp) AND command /= nop) THEN ASSERT false REPORT InstancePath & partID & ": Incorrect power up. Command" & " issued before power up complete." SEVERITY SeverityMode; END IF; -- Bank Decode CASE BAIn IS WHEN "00" => cur_bank := 0; BankString := " Bank-0 "; WHEN "01" => cur_bank := 1; BankString := " Bank-1 "; WHEN "10" => cur_bank := 2; BankString := " Bank-2 "; WHEN "11" => cur_bank := 3; BankString := " Bank-3 "; WHEN others => ASSERT false REPORT InstancePath & partID & ": Could not decode bank" & " selection - results may be incorrect." SEVERITY SeverityMode; END CASE; END IF; IF (rising_edge(CLKIn) AND CKEreg = '1') THEN ASSERT (not(Is_X(CSNegIn))) REPORT InstancePath & partID & ": Unusable value for CSNeg" SEVERITY SeverityMode; IF (CSNegIn = '1') THEN command := nop; END IF; -- by default data drive is Z, might get over written in one -- of the passes below DataDrive := (OTHERS => 'Z'); -- The Big State Machine banks : FOR bank IN 0 TO hi_bank LOOP CASE statebank(bank) IS⌨️ 快捷键说明
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