mt48lc8m8.vhd

vhdl cod for ram.For sp3e

    CLK_nwv <= To_UX01(CLK_ipd);
    CKE_nwv <= To_UX01(CKE_ipd);
    BA0_nwv <= To_UX01(BA0_ipd);
    BA1_nwv <= To_UX01(BA1_ipd);
    DQM_nwv <= To_UX01(DQM_ipd);
    DQ0_nwv <= To_UX01(DQ0_ipd);
    DQ1_nwv <= To_UX01(DQ1_ipd);
    DQ2_nwv <= To_UX01(DQ2_ipd);
    DQ3_nwv <= To_UX01(DQ3_ipd);
    DQ4_nwv <= To_UX01(DQ4_ipd);
    DQ5_nwv <= To_UX01(DQ5_ipd);
    DQ6_nwv <= To_UX01(DQ6_ipd);
    DQ7_nwv <= To_UX01(DQ7_ipd);
    A0_nwv <= To_UX01(A0_ipd);
    A1_nwv <= To_UX01(A1_ipd);
    A2_nwv <= To_UX01(A2_ipd);
    A3_nwv <= To_UX01(A3_ipd);
    A4_nwv <= To_UX01(A4_ipd);
    A5_nwv <= To_UX01(A5_ipd);
    A6_nwv <= To_UX01(A6_ipd);
    A7_nwv <= To_UX01(A7_ipd);
    A8_nwv <= To_UX01(A8_ipd);
    A9_nwv <= To_UX01(A9_ipd);
    A10_nwv <= To_UX01(A10_ipd);
    A11_nwv <= To_UX01(A11_ipd);

    ----------------------------------------------------------------------------
    -- Main Behavior Block
    ----------------------------------------------------------------------------
    Main : BLOCK

        PORT (
            BAIn            : IN    std_logic_vector(1 downto 0);
            DQMIn           : IN    std_ulogic := 'U';
            DataIn          : IN    std_logic_vector(HiDataBit downto 0);
            DataOut         : OUT   std_logic_vector(HiDataBit downto 0)
                                                     := (others => 'Z');
            CLKIn           : IN    std_ulogic := 'U';
            CKEIn           : IN    std_ulogic := 'U';
            AddressIn       : IN    std_logic_vector(HiAddrBit downto 0);
            WENegIn         : IN    std_ulogic := 'U';
            RASNegIn        : IN    std_ulogic := 'U';
            CSNegIn         : IN    std_ulogic := 'U';
            CASNegIn        : IN    std_ulogic := 'U'
        );
        PORT MAP (
            BAIn(0) => BA0_nwv,
            BAIn(1) => BA1_nwv,
            DQMIn   => DQM_nwv,
            DataOut(0) =>  DQ0,
            DataOut(1) =>  DQ1,
            DataOut(2) =>  DQ2,
            DataOut(3) =>  DQ3,
            DataOut(4) =>  DQ4,
            DataOut(5) =>  DQ5,
            DataOut(6) =>  DQ6,
            DataOut(7) =>  DQ7,
            DataIn(0) =>  DQ0_nwv,
            DataIn(1) =>  DQ1_nwv,
            DataIn(2) =>  DQ2_nwv,
            DataIn(3) =>  DQ3_nwv,
            DataIn(4) =>  DQ4_nwv,
            DataIn(5) =>  DQ5_nwv,
            DataIn(6) =>  DQ6_nwv,
            DataIn(7) =>  DQ7_nwv,
            CLKIn => CLK_nwv,
            CKEIn => CKE_nwv,
            AddressIn(0) => A0_nwv,
            AddressIn(1) => A1_nwv,
            AddressIn(2) => A2_nwv,
            AddressIn(3) => A3_nwv,
            AddressIn(4) => A4_nwv,
            AddressIn(5) => A5_nwv,
            AddressIn(6) => A6_nwv,
            AddressIn(7) => A7_nwv,
            AddressIn(8) => A8_nwv,
            AddressIn(9) => A9_nwv,
            AddressIn(10) => A10_nwv,
            AddressIn(11) => A11_nwv,
            WENegIn => WENeg_nwv,
            RASNegIn => RASNeg_nwv,
            CSNegIn => CSNeg_nwv,
            CASNegIn => CASNeg_nwv
        );

        -- Type definition for state machine
        TYPE mem_state IS (pwron,
                           precharge,
                           idle,
                           mode_set,
                           self_refresh,
                           self_refresh_rec,
                           auto_refresh,
                           pwrdwn,
                           bank_act,
                           bank_act_pwrdwn,
                           write,
                           write_suspend,
                           read,
                           read_suspend,
                           write_auto_pre,
                           read_auto_pre--,
                           --write_sec,
                           --read_sec
                          );

        TYPE statebanktype IS array (hi_bank downto 0) of mem_state;

        SIGNAL statebank : statebanktype;

        SIGNAL CAS_Lat   : NATURAL RANGE 2 to 3 := 3;
        SIGNAL D_zd      : std_logic_vector(HiDataBit DOWNTO 0);

    BEGIN
    PoweredUp <= true after tpowerup;
    ----------------------------------------------------------------------------
    -- Main Behavior Process
    ----------------------------------------------------------------------------
        Behavior :PROCESS(BAIn, DQMIn, DataIn, CLKIn, CKEIn, AddressIn, WENegIn,
                            RASNegIn, CSNegIn, CASNegIn, PoweredUp)

            -- Type definition for commands
            TYPE command_type is (desl,
                                  nop,
                                  bst,
                                  read,
                                  writ,
                                  act,
                                  pre,
                                  mrs,
                                  ref
                                 );

            -- Timing Check Variables
            VARIABLE Tviol_BA_CLK       : X01 := '0';
            VARIABLE TD_BA_CLK          : VitalTimingDataType;

            VARIABLE Tviol_D0_CLK       : X01 := '0';
            VARIABLE TD_D0_CLK          : VitalTimingDataType;

            VARIABLE Tviol_DQM_CLK     : X01 := '0';
            VARIABLE TD_DQM_CLK        : VitalTimingDataType;

            VARIABLE Tviol_CKE_CLK      : X01 := '0';
            VARIABLE TD_CKE_CLK         : VitalTimingDataType;

            VARIABLE Tviol_Address_CLK  : X01 := '0';
            VARIABLE TD_Address_CLK     : VitalTimingDataType;

            VARIABLE Tviol_WENeg_CLK    : X01 := '0';
            VARIABLE TD_WENeg_CLK       : VitalTimingDataType;

            VARIABLE Tviol_RASNeg_CLK   : X01 := '0';
            VARIABLE TD_RASNeg_CLK      : VitalTimingDataType;

            VARIABLE Tviol_CSNeg_CLK    : X01 := '0';
            VARIABLE TD_CSNeg_CLK       : VitalTimingDataType;

            VARIABLE Tviol_CASNeg_CLK   : X01 := '0';
            VARIABLE TD_CASNeg_CLK      : VitalTimingDataType;

            VARIABLE Pviol_CLK     : X01 := '0';
            VARIABLE PD_CLK        : VitalPeriodDataType := VitalPeriodDataInit;

            -- Memory array declaration
            TYPE MemStore IS ARRAY (0 to depth) OF INTEGER
                             RANGE  -2 TO (2**(HiDataBit+1))-1;

            TYPE MemBlock IS ARRAY (0 to 3) OF MemStore;
            TYPE Burst_type IS (sequential, interleave);
            TYPE Write_Burst_type IS (programmed, single);
            TYPE sequence IS ARRAY (0 to 7) OF NATURAL RANGE 0 to 7;
            TYPE seqtab IS ARRAY (0 to 7) OF sequence;
            TYPE MemLoc IS ARRAY (0 to 3) OF
                 std_logic_vector(HiAddrBit+HiColBit+1 DOWNTO 0);
            TYPE burst_counter IS ARRAY (0 to 3) OF NATURAL RANGE 0 to 257;
            TYPE StartAddr_type IS ARRAY (0 to 3) OF NATURAL RANGE 0 TO 7;
            TYPE Burst_Inc_type IS ARRAY (0 to 3) OF NATURAL RANGE 0 TO 8;
            TYPE BaseLoc_type IS ARRAY (0 to 3) OF NATURAL RANGE 0 TO depth;
            SUBTYPE OutWord IS std_logic_vector(HiDataBit DOWNTO 0);

            CONSTANT seq0 : sequence := (0 & 1 & 2 & 3 & 4 & 5 & 6 & 7);
            CONSTANT seq1 : sequence := (1 & 0 & 3 & 2 & 5 & 4 & 7 & 6);
            CONSTANT seq2 : sequence := (2 & 3 & 0 & 1 & 6 & 7 & 4 & 5);
            CONSTANT seq3 : sequence := (3 & 2 & 1 & 0 & 7 & 6 & 5 & 4);
            CONSTANT seq4 : sequence := (4 & 5 & 6 & 7 & 0 & 1 & 2 & 3);
            CONSTANT seq5 : sequence := (5 & 4 & 7 & 6 & 1 & 0 & 3 & 2);
            CONSTANT seq6 : sequence := (6 & 7 & 4 & 5 & 2 & 3 & 0 & 1);
            CONSTANT seq7 : sequence := (7 & 6 & 5 & 4 & 3 & 2 & 1 & 0);
            CONSTANT intab : seqtab := (seq0, seq1, seq2, seq3, seq4, seq5,
                                        seq6, seq7);

            FILE mem_file         : text IS mem_file_name;
            VARIABLE MemData      : MemBlock;
            VARIABLE file_bank    : NATURAL := 0;
            VARIABLE ind          : NATURAL := 0;
            VARIABLE buf          : line;

            VARIABLE MemAddr        : MemLoc;
            VARIABLE Location       : NATURAL RANGE 0 TO depth := 0;
            VARIABLE Location2      : NATURAL RANGE 0 TO depth := 0;
            VARIABLE BaseLoc        : BaseLoc_type;
            VARIABLE Burst_Inc      : Burst_Inc_type;
            VARIABLE StartAddr      : StartAddr_type;

            VARIABLE Burst_Length   : NATURAL RANGE 1 TO 8 := 1;
            VARIABLE Burst_Bits     : NATURAL RANGE 0 TO 3 := 0;
            VARIABLE Burst          : Burst_Type;
            VARIABLE Burst_Cnt      : burst_counter;
            VARIABLE WB             : Write_Burst_Type;

            VARIABLE command        : command_type;
            VARIABLE written        : boolean := false;
            VARIABLE chip_en        : boolean := false;
            VARIABLE cur_bank       : natural range 0 to hi_bank;

            VARIABLE ModeReg    : std_logic_vector(11 DOWNTO 0)
                                   := (OTHERS => 'X');

            VARIABLE Ref_Cnt      : NATURAL RANGE 0 TO 8192 := 0;
            VARIABLE next_ref     : TIME;
            VARIABLE BankString   : STRING(8 DOWNTO 1) := " Bank-X ";

            -- Functionality Results Variables
            VARIABLE Violation  : X01 := '0';
            VARIABLE DataDriveOut :  std_logic_vector(HiDataBit DOWNTO 0)
                                   := (OTHERS => 'Z');
            --Data out pipeline (CAS Latency)
            VARIABLE DataDrive  : OutWord;
            VARIABLE DataDrive1 : OutWord;
            VARIABLE DataDrive2 : OutWord;
            VARIABLE DataDrive3 : OutWord;

            --DQM Output enable pipeline
            VARIABLE DQM_reg1   : std_logic := '1';
            VARIABLE DQM_reg2   : std_logic := '1';

        PROCEDURE FixColumnAddress( bank : IN NATURAL RANGE 0 TO 3) IS
        BEGIN
            MemAddr(bank)(HiColBit downto 0) := (others => '0');
            MemAddr(bank)(HiColBit downto Burst_Bits) :=
                      AddressIn(HiColBit downto Burst_Bits); --
            IF (Burst_Bits > 0) THEN
                Burst_Inc(bank) :=
                         to_nat(AddressIn(Burst_Bits-1 downto 0));
            END IF;
            StartAddr(bank) := Burst_Inc(bank) mod 8;
            BaseLoc(bank) := to_nat(MemAddr(bank));
            Location := BaseLoc(bank) + Burst_Inc(bank);
        END PROCEDURE ;

        PROCEDURE ReadFromMem( bank : IN NATURAL RANGE 0 TO 3) IS
        BEGIN
            IF MemData(Bank)(Location) = -2 THEN
                DataDrive := (others => 'U');
            ELSIF MemData(Bank)(Location) = -1 THEN
                DataDrive := (others => 'X');
            ELSE
                DataDrive:=
                    to_slv(MemData(Bank)(Location),HiDataBit+1);
            END IF;
        END;

        PROCEDURE WriteToMem( bank : IN NATURAL RANGE 0 TO 3) IS
        BEGIN
            IF DQMIn = '0' THEN
                IF Violation = '0' THEN
                    MemData(Bank)(Location) := to_nat(DataIn);
                ELSE
                    MemData(Bank)(Location) := -1;
                END IF;
            END IF;
        END;

        PROCEDURE BurstCtrl( bank : IN NATURAL RANGE 0 TO 3) IS
        BEGIN
            IF (Burst = sequential) THEN
                Burst_Inc(bank) := (Burst_Inc(bank) + 1) MOD
                                    Burst_Length;
            ELSE
                Burst_Inc(bank) := intab(StartAddr(bank))
                                        (Burst_Cnt(bank));
            END IF;
            Location := BaseLoc(bank) + Burst_Inc(bank);
            Burst_Cnt(bank) := Burst_Cnt(bank) + 1;
        END;

        BEGIN
            --------------------------------------------------------------------
            -- Timing Check Section