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<!DOCTYPE FTML SYSTEM "ftml.dtd"><FTML><HEAD><TITLE>FMF Timing for cy7c1325b, gs840f18at, cy7c1325f Parts</TITLE><BODY><REVISION.HISTORY>version: | author: | mod date: | changes made: V1.0 D.Randjelovic 05 Dec 21 Initial release</REVISION.HISTORY><TIMESCALE>1ns</TIMESCALE><MODEL>cy7c1325<FMFTIME>cy7c1325b-117ac<SOURCE>Cypress 38-05146 Rev. *A Revised Jan. 18,2003</SOURCE><COMMENT>The values listed are for Vdd=3.135V to 3.6V, Vddq=3.3V, Ta=0 to +70 Celsius</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK DQA0 (2.5:5:7.5) (2.5:5:7.5) (2:2.8:3.5) (2.5:5:7.5) (2:2.8:3.5) (2.5:5:7.5)) (IOPATH CLK DQA1 (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0)) (IOPATH OENeg DQA0 ()()(1.2:2.4:3.5) (1.2:2.4:3.5)(1.2:2.4:3.5)(1.2:2.4:3.5)) (IOPATH OENeg DQA1 (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0)) )) (TIMINGCHECK (PERIOD (posedge CLK) (8.5)) (WIDTH (posedge CLK)(3)) (WIDTH (negedge CLK)(3)) (SETUP A0 CLK (2)) (SETUP DQA0 CLK (2)) (SETUP ADVNeg CLK (2)) (SETUP ADSCNeg CLK (2)) (SETUP BWANeg CLK (2)) (SETUP CE2 CLK (2)) (HOLD A0 CLK (0.5)) (HOLD DQA0 CLK (0.5)) (HOLD ADSCNeg CLK (0.5)) (HOLD BWANeg CLK (0.5)) (HOLD ADVNeg CLK (0.5)) (HOLD CE2 CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>cy7c1325b-100ac<SOURCE>Cypress 38-05146 Rev. *A Revised Jan. 18,2003</SOURCE>cy7c1325b-100bgc<SOURCE>Cypress 38-05146 Rev. *A Revised Jan. 18,2003</SOURCE>cy7c1325b-100ai<SOURCE>Cypress 38-05146 Rev. *A Revised Jan. 18,2003</SOURCE>cy7c1325b-100bgi<SOURCE>Cypress 38-05146 Rev. *A Revised Jan. 18,2003</SOURCE><COMMENT>The values listed are for Vdd=3.135V to 3.6V, Vddq=3.3V, Ta=-40 to +70 Celsius</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK DQA0 (2.7:5.4:8) (2.7:5.4:8) (2:2.8:3.5) (2.7:5.4:8) (2:2.8:3.5) (2.7:5.4:8)) (IOPATH CLK DQA1 (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0)) (IOPATH OENeg DQA0 ()()(1.2:2.4:3.5) (1.5:3:4.5)(1.2:2.4:3.5)(1.5:3:4.5)) (IOPATH OENeg DQA1 (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0)) )) (TIMINGCHECK (PERIOD (posedge CLK) (10)) (WIDTH (posedge CLK)(4)) (WIDTH (negedge CLK)(4)) (SETUP A0 CLK (2)) (SETUP DQA0 CLK (2)) (SETUP ADVNeg CLK (2)) (SETUP ADSCNeg CLK (2)) (SETUP BWANeg CLK (2)) (SETUP CE2 CLK (2)) (HOLD A0 CLK (0.5)) (HOLD DQA0 CLK (0.5)) (HOLD ADSCNeg CLK (0.5)) (HOLD BWANeg CLK (0.5)) (HOLD ADVNeg CLK (0.5)) (HOLD CE2 CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>gs840f18at-7.5<SOURCE>Giga Semiconductor, Inc. Datasheet 256K x 18 Sync Burst SRAM Rev. 1.07 May,2003</SOURCE>gs840f18at-7.5i<SOURCE>Giga Semiconductor, Inc. Datasheet 256K x 18 Sync Burst SRAM Rev. 1.07 May,2003</SOURCE><COMMENT>The values listed are for Vdd=3.135V to 3.6V, Ta=-40 to +85 Celsius</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK DQA0 (2.5:5:7.5) (2.5:5:7.5) (1.5:2.3:3) (2.5:5:7.5) (1.5:2.3:3) (2.5:5:7.5)) (IOPATH CLK DQA1 (3:3:3) (3:3:3) (3:3:3) (3:3:3) (3:3:3) (3:3:3)) (IOPATH OENeg DQA0 ()()(1:2:3) (1:2:3)(1:2:3)(1:2:3)) (IOPATH OENeg DQA1 (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0)) )) (TIMINGCHECK (PERIOD (posedge CLK) (8.5)) (WIDTH (posedge CLK)(1.3)) (WIDTH (negedge CLK)(1.5)) (SETUP A0 CLK (1.5)) (SETUP DQA0 CLK (1.5)) (SETUP ADVNeg CLK (1.5)) (SETUP ADSCNeg CLK (1.5)) (SETUP BWANeg CLK (1.5)) (SETUP CE2 CLK (1.5)) (HOLD A0 CLK (0.5)) (HOLD DQA0 CLK (0.5)) (HOLD ADSCNeg CLK (0.5)) (HOLD BWANeg CLK (0.5)) (HOLD ADVNeg CLK (0.5)) (HOLD CE2 CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>gs840f18at-8<SOURCE>Giga Semiconductor, Inc. Datasheet 256K x 18 Sync Burst SRAM Rev. 1.07 May,2003</SOURCE>gs840f18at-8i<SOURCE>Giga Semiconductor, Inc. Datasheet 256K x 18 Sync Burst SRAM Rev. 1.07 May,2003</SOURCE><COMMENT>The values listed are for Vdd=3.135V to 3.6V, Ta=-40 to +85 Celsius</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK DQA0 (2.7:5.4:8) (2.7:5.4:8) (1.5:2.3:3.2) (2.7:5.4:8) (1.5:2.3:3.2) (2.7:5.4:8)) (IOPATH CLK DQA1 (3:3:3) (3:3:3) (3:3:3) (3:3:3) (3:3:3) (3:3:3)) (IOPATH OENeg DQA0 ()()(1:2:3.2) (1:2:3.2)(1:2:3.2)(1:2:3.2)) (IOPATH OENeg DQA1 (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0)) )) (TIMINGCHECK (PERIOD (posedge CLK) (9)) (WIDTH (posedge CLK)(1.3)) (WIDTH (negedge CLK)(1.5)) (SETUP A0 CLK (1.5)) (SETUP DQA0 CLK (1.5)) (SETUP ADVNeg CLK (1.5)) (SETUP ADSCNeg CLK (1.5)) (SETUP BWANeg CLK (1.5)) (SETUP CE2 CLK (1.5)) (HOLD A0 CLK (0.5)) (HOLD DQA0 CLK (0.5)) (HOLD ADSCNeg CLK (0.5)) (HOLD BWANeg CLK (0.5)) (HOLD ADVNeg CLK (0.5)) (HOLD CE2 CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>gs840f18at-8.5<SOURCE>Giga Semiconductor, Inc. Datasheet 256K x 18 Sync Burst SRAM Rev. 1.07 May,2003</SOURCE>gs840f18at-8.5i<SOURCE>Giga Semiconductor, Inc. Datasheet 256K x 18 Sync Burst SRAM Rev. 1.07 May,2003</SOURCE><COMMENT>The values listed are for Vdd=3.135V to 3.6V, Ta=-40 to +85 Celsius</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK DQA0 (2.8:5.6:8.5) (2.8:5.6:8.5) (1.5:2.5:3.5) (2.8:5.6:8.5) (1.5:2.5:3.5) (2.8:5.6:8.5)) (IOPATH CLK DQA1 (3:3:3) (3:3:3) (3:3:3) (3:3:3) (3:3:3) (3:3:3)) (IOPATH OENeg DQA0 ()()(1.2:2.4:3.5) (1.2:2.4:3.5)(1.2:2.4:3.5)(1.2:2.4:3.5)) (IOPATH OENeg DQA1 (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0)) )) (TIMINGCHECK (PERIOD (posedge CLK) (10)) (WIDTH (posedge CLK)(1.3)) (WIDTH (negedge CLK)(1.5)) (SETUP A0 CLK (1.5)) (SETUP DQA0 CLK (1.5)) (SETUP ADVNeg CLK (1.5)) (SETUP ADSCNeg CLK (1.5)) (SETUP BWANeg CLK (1.5)) (SETUP CE2 CLK (1.5)) (HOLD A0 CLK (0.5)) (HOLD DQA0 CLK (0.5)) (HOLD ADSCNeg CLK (0.5)) (HOLD BWANeg CLK (0.5)) (HOLD ADVNeg CLK (0.5)) (HOLD CE2 CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>gs840f18at-10<SOURCE>Giga Semiconductor, Inc. Datasheet 256K x 18 Sync Burst SRAM Rev. 1.07 May,2003</SOURCE>gs840f18at-10i<SOURCE>Giga Semiconductor, Inc. Datasheet 256K x 18 Sync Burst SRAM Rev. 1.07 May,2003</SOURCE><COMMENT>The values listed are for Vdd=3.135V to 3.6V, Ta=-40 to +85 Celsius</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK DQA0 (3.3:6.6:10) (3.3:6.6:10) (1.5:2.6:3.8) (3.3:6.6:10) (1.5:2.6:3.8) (3.3:6.6:10)) (IOPATH CLK DQA1 (3:3:3) (3:3:3) (3:3:3) (3:3:3) (3:3:3) (3:3:3)) (IOPATH OENeg DQA0 ()()(1.3:2.6:3.8) (1.3:2.6:3.8)(1.3:2.6:3.8)(1.3:2.6:3.8)) (IOPATH OENeg DQA1 (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0)) )) (TIMINGCHECK (PERIOD (posedge CLK) (10)) (WIDTH (posedge CLK)(1.3)) (WIDTH (negedge CLK)(1.5)) (SETUP A0 CLK (1.5)) (SETUP DQA0 CLK (1.5)) (SETUP ADVNeg CLK (1.5)) (SETUP ADSCNeg CLK (1.5)) (SETUP BWANeg CLK (1.5)) (SETUP CE2 CLK (1.5)) (HOLD A0 CLK (0.5)) (HOLD DQA0 CLK (0.5)) (HOLD ADSCNeg CLK (0.5)) (HOLD BWANeg CLK (0.5)) (HOLD ADVNeg CLK (0.5)) (HOLD CE2 CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>gs840f18at-12<SOURCE>Giga Semiconductor, Inc. Datasheet 256K x 18 Sync Burst SRAM Rev. 1.07 May,2003</SOURCE>gs840f18at-12i<SOURCE>Giga Semiconductor, Inc. Datasheet 256K x 18 Sync Burst SRAM Rev. 1.07 May,2003</SOURCE><COMMENT>The values listed are for Vdd=3.135V to 3.6V, Ta=-40 to +85 Celsius</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK DQA0 (4:8:12) (4:8:12) (1.5:3.3:5) (4:8:12) (1.5:3.3:5) (4:8:12)) (IOPATH CLK DQA1 (3:3:3) (3:3:3) (3:3:3) (3:3:3) (3:3:3) (3:3:3)) (IOPATH OENeg DQA0 ()()(1.7:3.4:5) (1.7:3.4:5)(1.7:3.4:5)(1.7:3.4:5)) (IOPATH OENeg DQA1 (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0)) )) (TIMINGCHECK (PERIOD (posedge CLK) (15)) (WIDTH (posedge CLK)(1.3)) (WIDTH (negedge CLK)(1.5)) (SETUP A0 CLK (1.5)) (SETUP DQA0 CLK (1.5)) (SETUP ADVNeg CLK (1.5)) (SETUP ADSCNeg CLK (1.5)) (SETUP BWANeg CLK (1.5)) (SETUP CE2 CLK (1.5)) (HOLD A0 CLK (0.5)) (HOLD DQA0 CLK (0.5)) (HOLD ADSCNeg CLK (0.5)) (HOLD BWANeg CLK (0.5)) (HOLD ADVNeg CLK (0.5)) (HOLD CE2 CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>cy7c1325f-133ac<SOURCE>Cypress 38-05215 Rev. *A Revised Jan. 18,2003</SOURCE>cy7c1325f-133bgc<SOURCE>Cypress 38-05215 Rev. *A Revised Jan. 18,2003</SOURCE><COMMENT>The values listed are for Vdd=3.135V to 3.6V, Ta=0 to +70 Celsius</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK DQA0 (2.2:4.4:6.5) (2.2:4.4:6.5) (2:2.8:3.5) (2.2:4.4:6.5) (2:2.8:3.5) (2.2:4.4:6.5)) (IOPATH CLK DQA1 (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0)) (IOPATH OENeg DQA0 ()()(1.2:2.4:3.5) (1.2:2.4:3.5)(1.2:2.4:3.5)(1.2:2.4:3.5)) (IOPATH OENeg DQA1 (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0)) )) (TIMINGCHECK (PERIOD (posedge CLK) (7.5)) (WIDTH (posedge CLK)(2.5)) (WIDTH (negedge CLK)(2.5)) (SETUP A0 CLK (1.5)) (SETUP DQA0 CLK (1.5)) (SETUP ADVNeg CLK (1.5)) (SETUP ADSCNeg CLK (1.5)) (SETUP BWANeg CLK (1.5)) (SETUP CE2 CLK (1.5)) (HOLD A0 CLK (0.5)) (HOLD DQA0 CLK (0.5)) (HOLD ADSCNeg CLK (0.5)) (HOLD BWANeg CLK (0.5)) (HOLD ADVNeg CLK (0.5)) (HOLD CE2 CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>cy7c1325f-117ac<SOURCE>Cypress 38-05215 Rev. *A Revised Jan. 18,2003</SOURCE>cy7c1325f-117bgc<SOURCE>Cypress 38-05215 Rev. *A Revised Jan. 18,2003</SOURCE>cy7c1325f-117ai<SOURCE>Cypress 38-05215 Rev. *A Revised Jan. 18,2003</SOURCE>cy7c1325f-117bgi<SOURCE>Cypress 38-05215 Rev. *A Revised Jan. 18,2003</SOURCE><COMMENT>The values listed are for Vdd=3.135V to 3.6V, Ta=-40 to +70 Celsius</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK DQA0 (2.5:5:7.5) (2.5:5:7.5) (2:2.8:3.5) (2.5:5:7.5) (2:2.8:3.5) (2.5:5:7.5)) (IOPATH CLK DQA1 (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0)) (IOPATH OENeg DQA0 ()()(1.2:2.4:3.5) (1.2:2.4:3.5)(1.2:2.4:3.5)(1.2:2.4:3.5)) (IOPATH OENeg DQA1 (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0)) )) (TIMINGCHECK (PERIOD (posedge CLK) (8.5)) (WIDTH (posedge CLK)(3)) (WIDTH (negedge CLK)(3)) (SETUP A0 CLK (1.5)) (SETUP DQA0 CLK (2)) (SETUP ADVNeg CLK (2)) (SETUP ADSCNeg CLK (2)) (SETUP BWANeg CLK (2)) (SETUP CE2 CLK (2)) (HOLD A0 CLK (0.5)) (HOLD DQA0 CLK (0.5)) (HOLD ADSCNeg CLK (0.5)) (HOLD BWANeg CLK (0.5)) (HOLD ADVNeg CLK (0.5)) (HOLD CE2 CLK (0.5)) )</TIMING></FMFTIME><FMFTIME>cy7c1325f-100ac<SOURCE>Cypress 38-05215 Rev. *A Revised Jan. 18,2003</SOURCE>cy7c1325f-100bgc<SOURCE>Cypress 38-05215 Rev. *A Revised Jan. 18,2003</SOURCE>cy7c1325f-100ai<SOURCE>Cypress 38-05215 Rev. *A Revised Jan. 18,2003</SOURCE>cy7c1325f-100bgi<SOURCE>Cypress 38-05215 Rev. *A Revised Jan. 18,2003</SOURCE><COMMENT>The values listed are for Vdd=3.135V to 3.6V, Ta=-40 to +70 Celsius</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH CLK DQA0 (2.8:5.6:8.5) (2.8:5.6:8.5) (2:2.8:3.5) (2.8:5.6:8.5) (2:2.8:3.5) (2.8:5.6:8.5)) (IOPATH CLK DQA1 (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0)) (IOPATH OENeg DQA0 ()()(1.2:2.4:3.5) (1.2:2.4:3.5)(1.2:2.4:3.5)(1.2:2.4:3.5)) (IOPATH OENeg DQA1 (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0) (0:0:0)) )) (TIMINGCHECK (PERIOD (posedge CLK) (10)) (WIDTH (posedge CLK)(4)) (WIDTH (negedge CLK)(4)) (SETUP A0 CLK (1.5)) (SETUP DQA0 CLK (2)) (SETUP ADVNeg CLK (2)) (SETUP ADSCNeg CLK (2)) (SETUP BWANeg CLK (2)) (SETUP CE2 CLK (2)) (HOLD A0 CLK (0.5)) (HOLD DQA0 CLK (0.5)) (HOLD ADSCNeg CLK (0.5)) (HOLD BWANeg CLK (0.5)) (HOLD ADVNeg CLK (0.5)) (HOLD CE2 CLK (0.5)) )</TIMING></FMFTIME></BODY></FTML>⌨️ 快捷键说明
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