cy7c128.vhd

vhdl cod for ram.For sp3e

            AddressIn(3) => A3_ipd,
            AddressIn(4) => A4_ipd,
            AddressIn(5) => A5_ipd,
            AddressIn(6) => A6_ipd,
            AddressIn(7) => A7_ipd,
            AddressIn(8) => A8_ipd,
            AddressIn(9) => A9_ipd,
            AddressIn(10) => A10_ipd,
            OENegIn => OENeg_ipd,
            WENegIn => WENeg_ipd,
            CENegIn => CENeg_ipd
        );

        SIGNAL D_zd     : std_logic_vector(7 DOWNTO 0); 

    BEGIN 
        ------------------------------------------------------------------------
        -- Behavior Process
        ------------------------------------------------------------------------
        Behavior : PROCESS (OENegIn, WENegIn, CENegIn, AddressIn, DataIn)
                         
            -- Timing Check Variables
            VARIABLE Tviol_D0_WENeg: X01 := '0';
            VARIABLE TD_D0_WENeg   : VitalTimingDataType;

            VARIABLE Tviol_A0_WENeg: X01 := '0';
            VARIABLE TD_A0_WENeg   : VitalTimingDataType;

            VARIABLE Tviol_CENeg_WENeg : X01 := '0';
            VARIABLE TD_CENeg_WENeG    : VitalTimingDataType;

            VARIABLE Pviol_WENeg   : X01 := '0';
            VARIABLE PD_WENeg      : VitalPeriodDataType := VitalPeriodDataInit;

            -- Memory array declaration
            TYPE MemStore IS ARRAY (0 to 2047) OF NATURAL 
                             RANGE  0 TO 255;

            -- Functionality Results Variables
            VARIABLE Violation  : X01 := '0';
            VARIABLE DataDrive  : std_logic_vector(7 DOWNTO 0)
                                   := (OTHERS => 'X');
            VARIABLE DataTemp   : NATURAL RANGE 0 TO 255  := 0;
            VARIABLE Location   : NATURAL RANGE 0 TO 2047 := 0;
            VARIABLE MemData    : MemStore;

            -- No Weak Values Variables
            VARIABLE OENeg_nwv   : UX01 := 'X';
            VARIABLE WENeg_nwv   : UX01 := 'X';
            VARIABLE CENeg_nwv   : UX01 := 'X';

        BEGIN 
            OENeg_nwv   := To_UX01 (s => OENegIn);
            WENeg_nwv   := To_UX01 (s => WENegIn);
            CENeg_nwv   := To_UX01 (s => CENegIn);

            --------------------------------------------------------------------
            -- Timing Check Section
            --------------------------------------------------------------------
            IF (TimingChecksOn) THEN

                VitalSetupHoldCheck (
                    TestSignal      => DataIn,
                    TestSignalName  => "Data",
                    RefSignal       => WENeg,
                    RefSignalName   => "WENeg",
                    SetupHigh       => tsetup_D0_WENeg,
                    SetupLow        => tsetup_D0_WENeg,
                    HoldHigh        => thold_D0_WENeg,
                    HoldLow         => thold_D0_WENeg,
                    CheckEnabled    => (CENeg ='0' and OENeg ='1'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_D0_WENeg,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_D0_WENeg );

                VitalSetupHoldCheck (
                    TestSignal      => CENeg,
                    TestSignalName  => "CENeg",
                    RefSignal       => WENeg,
                    RefSignalName   => "WENeg",
                    SetupHigh       => tsetup_CENeg_WENeg,
                    SetupLow        => tsetup_CENeg_WENeg,
                    HoldHigh        => thold_CENeg_WENeg,
                    HoldLow         => thold_CENeg_WENeg,
                    CheckEnabled    => true,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_CENeg_WENeg,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_CENeg_WENeg);

                VitalSetupHoldCheck (
                    TestSignal      => AddressIn,
                    TestSignalName  => "Addr",
                    RefSignal       => WENeg,
                    RefSignalName   => "WENeg",
                    SetupHigh       => tsetup_A0_WENeg,
                    SetupLow        => tsetup_A0_WENeg,
                    HoldHigh        => thold_A0_WENeg,
                    HoldLow         => thold_A0_WENeg,
                    CheckEnabled    => (CENeg ='0'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_A0_WENeg,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_A0_WENeg );

                VitalPeriodPulseCheck (
                    TestSignal      =>  WENegIn,
                    TestSignalName  =>  "WENeg",
                    PulseWidthLow   =>  tpw_WENeg_negedge,
                    PeriodData      =>  PD_WENeg,
                    XOn             =>  XOn,
                    MsgOn           =>  MsgOn,
                    Violation       =>  Pviol_WENeg,
                    HeaderMsg       =>  InstancePath & PartID,
                    CheckEnabled    =>  TRUE );

                Violation := Pviol_WENeg OR Tviol_D0_WENeg OR Tviol_CENeg_WENeg
                             OR Tviol_A0_WENeg;

                ASSERT Violation = '0'
                    REPORT InstancePath & partID & ": simulation may be" &
                           " inaccurate due to timing violations"
                    SEVERITY SeverityMode;

            END IF; -- Timing Check Section

            --------------------------------------------------------------------
            -- Functional Section
            --------------------------------------------------------------------
            DataDrive := (OTHERS => 'Z');

            IF (CENeg_nwv = '0') THEN
                IF (OENeg_nwv = '0' OR WENeg_nwv = '0') THEN

                    Location := To_Nat(AddressIn);

                    IF (OENeg_nwv = '0' AND WENeg_nwv = '1') THEN
                        DataTemp  := MemData(Location);
                        DataDrive := To_slv(DataTemp, 8);
                    ELSE
                        DataTemp := To_Nat(DataIn);
                        MemData(Location) := DataTemp;
                    END IF;
                END IF;
            END IF;

            --------------------------------------------------------------------
            -- Output Section
            --------------------------------------------------------------------
            D_zd <= DataDrive;

        END PROCESS;                           

        ------------------------------------------------------------------------
        -- Path Delay Processes generated as a function of data width
        ------------------------------------------------------------------------
        DataOut_Width : FOR i IN 7 DOWNTO 0 GENERATE
            DataOut_Delay : PROCESS (D_zd(i)) 
                VARIABLE D_GlitchData:VitalGlitchDataArrayType(7 Downto 0);
            BEGIN
                VitalPathDelay01Z (
                    OutSignal       => DataOut(i),
                    OutSignalName   => "Data",
                    OutTemp         => D_zd(i),
                    Mode            => OnEvent, 
                    GlitchData      => D_GlitchData(i),
                    Paths           => (     
                        0 => (InputChangeTime => OENeg_ipd'LAST_EVENT,
                              PathDelay       => tpd_OENeg_D0,
                              PathCondition   => TRUE),   
                        1 => (InputChangeTime => CENeg_ipd'LAST_EVENT,
                              PathDelay       => tpd_CENeg_D0,
                              PathCondition   => TRUE),   
                        2 => (InputChangeTime => AddressIn(0)'LAST_EVENT,
                              PathDelay => VitalExtendToFillDelay(tpd_A0_D0),
                              PathCondition   => TRUE),
                        3 => (InputChangeTime => AddressIn(1)'LAST_EVENT,
                              PathDelay => VitalExtendToFillDelay(tpd_A0_D0),
                              PathCondition   => TRUE),
                        4 => (InputChangeTime => AddressIn(2)'LAST_EVENT,
                              PathDelay => VitalExtendToFillDelay(tpd_A0_D0),
                              PathCondition   => TRUE),
                        5 => (InputChangeTime => AddressIn(3)'LAST_EVENT,
                              PathDelay => VitalExtendToFillDelay(tpd_A0_D0),
                              PathCondition   => TRUE),
                        6 => (InputChangeTime => AddressIn(4)'LAST_EVENT,
                              PathDelay => VitalExtendToFillDelay(tpd_A0_D0),
                              PathCondition   => TRUE),
                        7 => (InputChangeTime => AddressIn(5)'LAST_EVENT,
                              PathDelay => VitalExtendToFillDelay(tpd_A0_D0),
                              PathCondition   => TRUE),
                        8 => (InputChangeTime => AddressIn(6)'LAST_EVENT,
                              PathDelay => VitalExtendToFillDelay(tpd_A0_D0),
                              PathCondition   => TRUE),
                        9 => (InputChangeTime => AddressIn(7)'LAST_EVENT,
                              PathDelay => VitalExtendToFillDelay(tpd_A0_D0),
                              PathCondition   => TRUE),
                       10 => (InputChangeTime => AddressIn(8)'LAST_EVENT,
                              PathDelay => VitalExtendToFillDelay(tpd_A0_D0),
                              PathCondition   => TRUE),
                       11 => (InputChangeTime => AddressIn(9)'LAST_EVENT,
                              PathDelay => VitalExtendToFillDelay(tpd_A0_D0),
                              PathCondition   => TRUE),
                       12 => (InputChangeTime => AddressIn(10)'LAST_EVENT,
                              PathDelay => VitalExtendToFillDelay(tpd_A0_D0),
                              PathCondition   => TRUE)
                    )
                );

            END PROCESS;                           
        END GENERATE;

    END BLOCK;
END vhdl_behavioral;