idt70t3589dr.vhd

vhdl cod for ram.For sp3e

    SIGNAL BE3NegR_ipd      : std_ulogic := 'U';
    SIGNAL ZZR_ipd          : std_ulogic := 'U';

    SIGNAL left_in          : std_ulogic := '0';
    SIGNAL left             : std_ulogic := '0';
    SIGNAL right_in         : std_ulogic := '0';
    SIGNAL right            : std_ulogic := '0';

BEGIN
    ---------------------------------------------------------------------------
    -- Internal Delays
    ---------------------------------------------------------------------------
    -- Artificial VITAL primitives to incorporate internal delays
    TCCS : VitalBuf (left , left_in , (VitalZeroDelay,tdevice_TCO)); --left
    TCCS1: VitalBuf (right, right_in, (VitalZeroDelay,tdevice_TCO)); --right

    ---------------------------------------------------------------------------
    -- Wire Delays
    ---------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN
        w_1   : VitalWireDelay (OENegL_ipd    , OENegL    , tipd_OENegL );
        w_2   : VitalWireDelay (A0L_ipd       , A0L       , tipd_A0L  );
        w_3   : VitalWireDelay (A1L_ipd       , A1L       , tipd_A1L  );
        w_4   : VitalWireDelay (A2L_ipd       , A2L       , tipd_A2L  );
        w_5   : VitalWireDelay (A3L_ipd       , A3L       , tipd_A3L  );
        w_6   : VitalWireDelay (A4L_ipd       , A4L       , tipd_A4L  );
        w_7   : VitalWireDelay (A5L_ipd       , A5L       , tipd_A5L  );
        w_8   : VitalWireDelay (A6L_ipd       , A6L       , tipd_A6L  );
        w_9   : VitalWireDelay (A7L_ipd       , A7L       , tipd_A7L  );
        w_10  : VitalWireDelay (A8L_ipd       , A8L       , tipd_A8L  );
        w_11  : VitalWireDelay (A9L_ipd       , A9L       , tipd_A9L  );
        w_12  : VitalWireDelay (A10L_ipd      , A10L      , tipd_A10L );
        w_13  : VitalWireDelay (A11L_ipd      , A11L      , tipd_A11L );
        w_14  : VitalWireDelay (A12L_ipd      , A12L      , tipd_A12L );
        w_15  : VitalWireDelay (A13L_ipd      , A13L      , tipd_A13L );
        w_16  : VitalWireDelay (A14L_ipd      , A14L      , tipd_A14L );
        w_17  : VitalWireDelay (A15L_ipd      , A15L      , tipd_A15L );
        w_20  : VitalWireDelay (IO0L_ipd      , IO0L      , tipd_IO0L );
        w_21  : VitalWireDelay (IO1L_ipd      , IO1L      , tipd_IO1L );
        w_22  : VitalWireDelay (IO2L_ipd      , IO2L      , tipd_IO2L );
        w_23  : VitalWireDelay (IO3L_ipd      , IO3L      , tipd_IO3L );
        w_24  : VitalWireDelay (IO4L_ipd      , IO4L      , tipd_IO4L );
        w_25  : VitalWireDelay (IO5L_ipd      , IO5L      , tipd_IO5L );
        w_26  : VitalWireDelay (IO6L_ipd      , IO6L      , tipd_IO6L );
        w_27  : VitalWireDelay (IO7L_ipd      , IO7L      , tipd_IO7L );
        w_28  : VitalWireDelay (IO8L_ipd      , IO8L      , tipd_IO8L );
        w_29  : VitalWireDelay (IO9L_ipd      , IO9L      , tipd_IO9L );
        w_30  : VitalWireDelay (IO10L_ipd     , IO10L     , tipd_IO10L);
        w_31  : VitalWireDelay (IO11L_ipd     , IO11L     , tipd_IO11L);
        w_32  : VitalWireDelay (IO12L_ipd     , IO12L     , tipd_IO12L);
        w_33  : VitalWireDelay (IO13L_ipd     , IO13L     , tipd_IO13L);
        w_34  : VitalWireDelay (IO14L_ipd     , IO14L     , tipd_IO14L);
        w_35  : VitalWireDelay (IO15L_ipd     , IO15L     , tipd_IO15L);
        w_36  : VitalWireDelay (IO16L_ipd     , IO16L     , tipd_IO16L);
        w_37  : VitalWireDelay (IO17L_ipd     , IO17L     , tipd_IO17L);
        w_38  : VitalWireDelay (IO18L_ipd     , IO18L     , tipd_IO18L);
        w_39  : VitalWireDelay (IO19L_ipd     , IO19L     , tipd_IO19L);
        w_40  : VitalWireDelay (IO20L_ipd     , IO20L     , tipd_IO20L);
        w_41  : VitalWireDelay (IO21L_ipd     , IO21L     , tipd_IO21L);
        w_42  : VitalWireDelay (IO22L_ipd     , IO22L     , tipd_IO22L);
        w_43  : VitalWireDelay (IO23L_ipd     , IO23L     , tipd_IO23L);
        w_44  : VitalWireDelay (IO24L_ipd     , IO24L     , tipd_IO24L);
        w_45  : VitalWireDelay (IO25L_ipd     , IO25L     , tipd_IO25L);
        w_46  : VitalWireDelay (IO26L_ipd     , IO26L     , tipd_IO26L);
        w_47  : VitalWireDelay (IO27L_ipd     , IO27L     , tipd_IO27L);
        w_48  : VitalWireDelay (IO28L_ipd     , IO28L     , tipd_IO28L);
        w_49  : VitalWireDelay (IO29L_ipd     , IO29L     , tipd_IO29L);
        w_50  : VitalWireDelay (IO30L_ipd     , IO30L     , tipd_IO30L);
        w_51  : VitalWireDelay (IO31L_ipd     , IO31L     , tipd_IO31L);
        w_52  : VitalWireDelay (IO32L_ipd     , IO32L     , tipd_IO32L);
        w_53  : VitalWireDelay (IO33L_ipd     , IO33L     , tipd_IO33L);
        w_54  : VitalWireDelay (IO34L_ipd     , IO34L     , tipd_IO34L);
        w_55  : VitalWireDelay (IO35L_ipd     , IO35L     , tipd_IO35L);
        w_56  : VitalWireDelay (CE0NegL_ipd   , CE0NegL   , tipd_CE0NegL   );
        w_57  : VitalWireDelay (CE1L_ipd      , CE1L      , tipd_CE1L      );
        w_58  : VitalWireDelay (RWL_ipd       , RWL       , tipd_RWL       );
        w_59  : VitalWireDelay (CLKL_ipd      , CLKL      , tipd_CLKL      );
        w_60  : VitalWireDelay (ADSNegL_ipd   , ADSNegL   , tipd_ADSNegL   );
        w_61  : VitalWireDelay (CNTENNegL_ipd , CNTENNegL , tipd_CNTENNegL );
        w_62  : VitalWireDelay (REPEATNegL_ipd, REPEATNegL, tipd_REPEATNegL);
        w_63  : VitalWireDelay (BE0NegL_ipd   , BE0NegL   , tipd_BE0NegL   );
        w_64  : VitalWireDelay (BE1NegL_ipd   , BE1NegL   , tipd_BE1NegL   );
        w_65  : VitalWireDelay (BE2NegL_ipd   , BE2NegL   , tipd_BE2NegL   );
        w_66  : VitalWireDelay (BE3NegL_ipd   , BE3NegL   , tipd_BE3NegL   );
        w_67  : VitalWireDelay (ZZL_ipd       , ZZL       , tipd_ZZL       );
        w_68  : VitalWireDelay (A0R_ipd       , A0R       , tipd_A0R       );
        w_69  : VitalWireDelay (A1R_ipd       , A1R       , tipd_A1R       );
        w_70  : VitalWireDelay (A2R_ipd       , A2R       , tipd_A2R       );
        w_71  : VitalWireDelay (A3R_ipd       , A3R       , tipd_A3R       );
        w_72  : VitalWireDelay (A4R_ipd       , A4R       , tipd_A4R       );
        w_73  : VitalWireDelay (A5R_ipd       , A5R       , tipd_A5R       );
        w_74  : VitalWireDelay (A6R_ipd       , A6R       , tipd_A6R );
        w_75  : VitalWireDelay (A7R_ipd       , A7R       , tipd_A7R );
        w_76  : VitalWireDelay (A8R_ipd       , A8R       , tipd_A8R );
        w_77  : VitalWireDelay (A9R_ipd       , A9R       , tipd_A9R );
        w_78  : VitalWireDelay (A10R_ipd      , A10R      , tipd_A10R);
        w_79  : VitalWireDelay (A11R_ipd      , A11R      , tipd_A11R);
        w_80  : VitalWireDelay (A12R_ipd      , A12R      , tipd_A12R);
        w_81  : VitalWireDelay (A13R_ipd      , A13R      , tipd_A13R);
        w_82  : VitalWireDelay (A14R_ipd      , A14R      , tipd_A14R);
        w_83  : VitalWireDelay (A15R_ipd      , A15R      , tipd_A15R);
        w_86  : VitalWireDelay (IO0R_ipd      , IO0R      , tipd_IO0R);
        w_87  : VitalWireDelay (IO1R_ipd      , IO1R      , tipd_IO1R);
        w_88  : VitalWireDelay (IO2R_ipd      , IO2R      , tipd_IO2R);
        w_89  : VitalWireDelay (IO3R_ipd      , IO3R      , tipd_IO3R);
        w_90  : VitalWireDelay (IO4R_ipd      , IO4R      , tipd_IO4R);
        w_91  : VitalWireDelay (IO5R_ipd      , IO5R      , tipd_IO5R);
        w_92  : VitalWireDelay (IO6R_ipd      , IO6R      , tipd_IO6R );
        w_93  : VitalWireDelay (IO7R_ipd      , IO7R      , tipd_IO7R );
        w_94  : VitalWireDelay (IO8R_ipd      , IO8R      , tipd_IO8R );
        w_95  : VitalWireDelay (IO9R_ipd      , IO9R      , tipd_IO9R );
        w_96  : VitalWireDelay (IO10R_ipd     , IO10R     , tipd_IO10R);
        w_97  : VitalWireDelay (IO11R_ipd     , IO11R     , tipd_IO11R);
        w_98  : VitalWireDelay (IO12R_ipd     , IO12R     , tipd_IO12R);
        w_99  : VitalWireDelay (IO13R_ipd     , IO13R     , tipd_IO13R);
        w_100 : VitalWireDelay (IO14R_ipd     , IO14R     , tipd_IO14R);
        w_101 : VitalWireDelay (IO15R_ipd     , IO15R     , tipd_IO15R);
        w_102 : VitalWireDelay (IO16R_ipd     , IO16R     , tipd_IO16R);
        w_103 : VitalWireDelay (IO17R_ipd     , IO17R     , tipd_IO17R);
        w_104 : VitalWireDelay (IO18R_ipd     , IO18R     , tipd_IO18R);
        w_106 : VitalWireDelay (IO19R_ipd     , IO19R     , tipd_IO19R);
        w_107 : VitalWireDelay (IO20R_ipd     , IO20R     , tipd_IO20R);
        w_108 : VitalWireDelay (IO21R_ipd     , IO21R     , tipd_IO21R);
        w_109 : VitalWireDelay (IO22R_ipd     , IO22R     , tipd_IO22R);
        w_110 : VitalWireDelay (IO23R_ipd     , IO23R     , tipd_IO23R);
        w_111 : VitalWireDelay (IO24R_ipd     , IO24R     , tipd_IO24R);
        w_112 : VitalWireDelay (IO25R_ipd     , IO25R     , tipd_IO25R);
        w_113 : VitalWireDelay (IO26R_ipd     , IO26R     , tipd_IO26R);
        w_114 : VitalWireDelay (IO27R_ipd     , IO27R     , tipd_IO27R);
        w_115 : VitalWireDelay (IO28R_ipd     , IO28R     , tipd_IO28R);
        w_116 : VitalWireDelay (IO29R_ipd     , IO29R     , tipd_IO29R);
        w_117 : VitalWireDelay (IO30R_ipd     , IO30R     , tipd_IO30R);
        w_118 : VitalWireDelay (IO31R_ipd     , IO31R     , tipd_IO31R);
        w_119 : VitalWireDelay (IO32R_ipd     , IO32R     , tipd_IO32R);
        w_120 : VitalWireDelay (IO33R_ipd     , IO33R     , tipd_IO33R);
        w_121 : VitalWireDelay (IO34R_ipd     , IO34R     , tipd_IO34R);
        w_122 : VitalWireDelay (IO35R_ipd     , IO35R     , tipd_IO35R);
        w_123 : VitalWireDelay (CE0NegR_ipd   , CE0NegR   , tipd_CE0NegR);
        w_124 : VitalWireDelay (CE1R_ipd      , CE1R      , tipd_CE1R );
        w_125 : VitalWireDelay (RWR_ipd       , RWR       , tipd_RWR   );
        w_126 : VitalWireDelay (CLKR_ipd      , CLKR      , tipd_CLKR );
        w_127 : VitalWireDelay (ADSNegR_ipd   , ADSNegR   , tipd_ADSNegR);
        w_128 : VitalWireDelay (CNTENNegR_ipd , CNTENNegR , tipd_CNTENNegR);
        w_129 : VitalWireDelay (REPEATNegR_ipd, REPEATNegR, tipd_REPEATNegR);
        w_130 : VitalWireDelay (BE0NegR_ipd   , BE0NegR   , tipd_BE0NegR);
        w_131 : VitalWireDelay (BE1NegR_ipd   , BE1NegR   , tipd_BE1NegR);
        w_132 : VitalWireDelay (BE2NegR_ipd   , BE2NegR   , tipd_BE2NegR);
        w_133 : VitalWireDelay (BE3NegR_ipd   , BE3NegR   , tipd_BE3NegR);
        w_134 : VitalWireDelay (ZZR_ipd       , ZZR       , tipd_ZZR    );
        w_139 : VitalWireDelay (OENegR_ipd    , OENegR    , tipd_OENegR );
        w_140 : VitalWireDelay (PLNegL_ipd    , PLNegL    , tipd_PLNegL );
        w_141 : VitalWireDelay (PLNegR_ipd    , PLNegR    , tipd_PLNegR );

    END BLOCK;

    ---------------------------------------------------------------------------
    -- Main Behavior Block
    ---------------------------------------------------------------------------
    Behavior: BLOCK
    PORT (
        AddressL          : IN    std_logic_vector(HiAddrBit downto 0);
        DataInL           : IN    std_logic_vector(35 downto 0);
        DataOutL          : OUT   std_logic_vector(35 downto 0);
        RWL               : IN    std_logic;
        CEL               : IN    std_logic_vector(1 downto 0);
        OEL               : IN    std_logic;
        ClockL            : IN    std_logic;
        PLNegL            : IN    std_logic;
        ADSNegL           : IN    std_logic;
        CNTENNegL         : IN    std_logic;
        REPEATNegL        : IN    std_logic;
        BENegL            : IN    std_logic_vector(3 downto 0);
        ZZL               : IN    std_logic;
        INTNegL           : OUT   std_logic;
        COLNegL           : OUT   std_logic;

        AddressR          : IN    std_logic_vector(HiAddrBit downto 0);
        DataInR           : IN    std_logic_vector(35 downto 0);
        DataOutR          : OUT   std_logic_vector(35 downto 0);
        RWR               : IN    std_logic;
        CER               : IN    std_logic_vector(1 downto 0);
        OER               : IN    std_logic;
        ClockR            : IN    std_logic;
        PLNegR            : IN    std_logic;
        ADSNegR           : IN    std_logic;
        CNTENNegR         : IN    std_logic;
        REPEATNegR        : IN    std_logic;
        BENegR            : IN    std_logic_vector(3 downto 0);
        ZZR               : IN    std_logic;
        INTNegR           : OUT   std_logic;
        COLNegR           : OUT   std_logic
    );
    PORT MAP (
        AddressL(0 )    => A0L_ipd   ,
        AddressL(1 )    => A1L_ipd   ,
        AddressL(2 )    => A2L_ipd   ,
        AddressL(3 )    => A3L_ipd   ,
        AddressL(4 )    => A4L_ipd   ,
        AddressL(5 )    => A5L_ipd   ,
        AddressL(6 )    => A6L_ipd   ,
        AddressL(7 )    => A7L_ipd   ,
        AddressL(8 )    => A8L_ipd   ,
        AddressL(9 )    => A9L_ipd   ,
        AddressL(10)    => A10L_ipd ,
        AddressL(11)    => A11L_ipd ,
        AddressL(12)    => A12L_ipd ,
        AddressL(13)    => A13L_ipd ,
        AddressL(14)    => A14L_ipd ,
        AddressL(15)    => A15L_ipd ,

        DataInL(0 )     => IO0L_ipd    ,
        DataInL(1 )     => IO1L_ipd    ,
        DataInL(2 )     => IO2L_ipd    ,
        DataInL(3 )     => IO3L_ipd    ,
        DataInL(4 )     => IO4L_ipd    ,
        DataInL(5 )     => IO5L_ipd    ,
        DataInL(6 )     => IO6L_ipd    ,
        DataInL(7 )     => IO7L_ipd    ,
        DataInL(8 )     => IO8L_ipd    ,
        DataInL(9 )     => IO9L_ipd    ,
        DataInL(10)     => IO10L_ipd   ,
        DataInL(11)     => IO11L_ipd   ,
        DataInL(12)     => IO12L_ipd   ,
        DataInL(13)     => IO13L_ipd   ,
        DataInL(14)     => IO14L_ipd   ,
        DataInL(15)     => IO15L_ipd   ,
        DataInL(16)     => IO16L_ipd   ,
        DataInL(17)     => IO17L_ipd   ,
        DataInL(18)     => IO18L_ipd   ,
        DataInL(19)     => IO19L_ipd   ,
        DataInL(20)     => IO20L_ipd   ,
        DataInL(21)     => IO21L_ipd   ,
        DataInL(22)     => IO22L_ipd   ,
        DataInL(23)     => IO23L_ipd   ,
        DataInL(24)     => IO24L_ipd   ,
        DataInL(25)     => IO25L_ipd   ,
        DataInL(26)     => IO26L_ipd   ,
        DataInL(27)     => IO27L_ipd   ,
        DataInL(28)     => IO28L_ipd   ,
        DataInL(29)     => IO29L_ipd   ,
        DataInL(30)     => IO30L_ipd   ,
        DataInL(31)     => IO31L_ipd   ,
        DataInL(32)     => IO32L_ipd   ,
        DataInL(33)     => IO33L_ipd   ,
        DataInL(34)     => IO34L_ipd   ,
        DataInL(35)     => IO35L_ipd   ,

        DataOutL(0 )    => IO0L    ,
        DataOutL(1 )    => IO1L    ,
        DataOutL(2 )    => IO2L    ,
        DataOutL(3 )    => IO3L    ,
        DataOutL(4 )    => IO4L    ,
        DataOutL(5 )    => IO5L    ,
        DataOutL(6 )    => IO6L    ,
        DataOutL(7 )    => IO7L    ,
        DataOutL(8 )    => IO8L    ,
        DataOutL(9 )    => IO9L    ,
        DataOutL(10)    => IO10L   ,
        DataOutL(11)    => IO11L   ,
        DataOutL(12)    => IO12L   ,
        DataOutL(13)    => IO13L   ,
        DataOutL(14)    => IO14L   ,