idt70t3589dr.vhd

vhdl cod for ram.For sp3e

        IO17L            : INOUT    std_logic := 'U';
        IO18L            : INOUT    std_logic := 'U';
        IO19L            : INOUT    std_logic := 'U';
        IO20L            : INOUT    std_logic := 'U';
        IO21L            : INOUT    std_logic := 'U';
        IO22L            : INOUT    std_logic := 'U';
        IO23L            : INOUT    std_logic := 'U';
        IO24L            : INOUT    std_logic := 'U';
        IO25L            : INOUT    std_logic := 'U';
        IO26L            : INOUT    std_logic := 'U';
        IO27L            : INOUT    std_logic := 'U';
        IO28L            : INOUT    std_logic := 'U';
        IO29L            : INOUT    std_logic := 'U';
        IO30L            : INOUT    std_logic := 'U';
        IO31L            : INOUT    std_logic := 'U';
        IO32L            : INOUT    std_logic := 'U';
        IO33L            : INOUT    std_logic := 'U';
        IO34L            : INOUT    std_logic := 'U';
        IO35L            : INOUT    std_logic := 'U';
        --Left port control
        CE0NegL          : IN    std_logic := 'U';
        CE1L             : IN    std_logic := 'U';
        OENegL           : IN    std_logic := 'U';
        RWL              : IN    std_logic := 'U';
        CLKL             : IN    std_logic := 'U';
        PLNegL           : IN    std_logic := 'U';
        ADSNegL          : IN    std_logic := 'U';
        CNTENNegL        : IN    std_logic := 'U';
        REPEATNegL       : IN    std_logic := 'U';
        BE0NegL          : IN    std_logic := 'U';
        BE1NegL          : IN    std_logic := 'U';
        BE2NegL          : IN    std_logic := 'U';
        BE3NegL          : IN    std_logic := 'U';
        ZZL              : IN    std_logic := 'U';
        --Left port outputs
        INTNegL          : OUT   std_logic := 'U';   --INterrupt
        COLNegL          : OUT   std_logic := 'U';   --Collision Alert

        --Right port Address lines
        A0R              : IN    std_logic := 'U';
        A1R              : IN    std_logic := 'U';
        A2R              : IN    std_logic := 'U';
        A3R              : IN    std_logic := 'U';
        A4R              : IN    std_logic := 'U';
        A5R              : IN    std_logic := 'U';
        A6R              : IN    std_logic := 'U';
        A7R              : IN    std_logic := 'U';
        A8R              : IN    std_logic := 'U';
        A9R              : IN    std_logic := 'U';
        A10R             : IN    std_logic := 'U';
        A11R             : IN    std_logic := 'U';
        A12R             : IN    std_logic := 'U';
        A13R             : IN    std_logic := 'U';
        A14R             : IN    std_logic := 'U';
        A15R             : IN    std_logic := 'U';
        --Right port IO lines
        IO0R             : INOUT    std_logic := 'U';
        IO1R             : INOUT    std_logic := 'U';
        IO2R             : INOUT    std_logic := 'U';
        IO3R             : INOUT    std_logic := 'U';
        IO4R             : INOUT    std_logic := 'U';
        IO5R             : INOUT    std_logic := 'U';
        IO6R             : INOUT    std_logic := 'U';
        IO7R             : INOUT    std_logic := 'U';
        IO8R             : INOUT    std_logic := 'U';
        IO9R             : INOUT    std_logic := 'U';
        IO10R            : INOUT    std_logic := 'U';
        IO11R            : INOUT    std_logic := 'U';
        IO12R            : INOUT    std_logic := 'U';
        IO13R            : INOUT    std_logic := 'U';
        IO14R            : INOUT    std_logic := 'U';
        IO15R            : INOUT    std_logic := 'U';
        IO16R            : INOUT    std_logic := 'U';
        IO17R            : INOUT    std_logic := 'U';
        IO18R            : INOUT    std_logic := 'U';
        IO19R            : INOUT    std_logic := 'U';
        IO20R            : INOUT    std_logic := 'U';
        IO21R            : INOUT    std_logic := 'U';
        IO22R            : INOUT    std_logic := 'U';
        IO23R            : INOUT    std_logic := 'U';
        IO24R            : INOUT    std_logic := 'U';
        IO25R            : INOUT    std_logic := 'U';
        IO26R            : INOUT    std_logic := 'U';
        IO27R            : INOUT    std_logic := 'U';
        IO28R            : INOUT    std_logic := 'U';
        IO29R            : INOUT    std_logic := 'U';
        IO30R            : INOUT    std_logic := 'U';
        IO31R            : INOUT    std_logic := 'U';
        IO32R            : INOUT    std_logic := 'U';
        IO33R            : INOUT    std_logic := 'U';
        IO34R            : INOUT    std_logic := 'U';
        IO35R            : INOUT    std_logic := 'U';
        --Right port controml lines
        CE0NegR          : IN    std_logic := 'U';
        CE1R             : IN    std_logic := 'U';
        OENegR           : IN    std_logic := 'U';
        RWR              : IN    std_logic := 'U';
        CLKR             : IN    std_logic := 'U';
        PLNegR           : IN    std_logic := 'U';
        ADSNegR          : IN    std_logic := 'U';
        CNTENNegR        : IN    std_logic := 'U';
        REPEATNegR       : IN    std_logic := 'U';
        BE0NegR          : IN    std_logic := 'U';
        BE1NegR          : IN    std_logic := 'U';
        BE2NegR          : IN    std_logic := 'U';
        BE3NegR          : IN    std_logic := 'U';
        ZZR              : IN    std_logic := 'U';
        --Right port outputs
        INTNegR          : OUT   std_logic := 'U';   --INterrupt
        COLNegR          : OUT   std_logic := 'U'   --Collision Alert
    );
    ATTRIBUTE VITAL_LEVEL0 of idt70t3589dr : ENTITY IS TRUE;
END idt70t3589dr;

-------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
-------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of idt70t3589dr IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT partID         : STRING  := "idt70t3589dr";
    CONSTANT HiAddrBit      : NATURAL := 15;
    CONSTANT MaxData        : NATURAL := 511;
    CONSTANT MemSize        : NATURAL := (2**(HiAddrBit+1))-1;--0xFFFF=64K
    CONSTANT MailBoxL       : NATURAL := MemSize-1;
    CONSTANT MailBoxR       : NATURAL := MemSize;

    SIGNAL A0L_ipd          : std_ulogic := 'U';
    SIGNAL A1L_ipd          : std_ulogic := 'U';
    SIGNAL A2L_ipd          : std_ulogic := 'U';
    SIGNAL A3L_ipd          : std_ulogic := 'U';
    SIGNAL A4L_ipd          : std_ulogic := 'U';
    SIGNAL A5L_ipd          : std_ulogic := 'U';
    SIGNAL A6L_ipd          : std_ulogic := 'U';
    SIGNAL A7L_ipd          : std_ulogic := 'U';
    SIGNAL A8L_ipd          : std_ulogic := 'U';
    SIGNAL A9L_ipd          : std_ulogic := 'U';
    SIGNAL A10L_ipd         : std_ulogic := 'U';
    SIGNAL A11L_ipd         : std_ulogic := 'U';
    SIGNAL A12L_ipd         : std_ulogic := 'U';
    SIGNAL A13L_ipd         : std_ulogic := 'U';
    SIGNAL A14L_ipd         : std_ulogic := 'U';
    SIGNAL A15L_ipd         : std_ulogic := 'U';
    --Left port IO lines
    SIGNAL IO0L_ipd         : std_ulogic := 'U';
    SIGNAL IO1L_ipd         : std_ulogic := 'U';
    SIGNAL IO2L_ipd         : std_ulogic := 'U';
    SIGNAL IO3L_ipd         : std_ulogic := 'U';
    SIGNAL IO4L_ipd         : std_ulogic := 'U';
    SIGNAL IO5L_ipd         : std_ulogic := 'U';
    SIGNAL IO6L_ipd         : std_ulogic := 'U';
    SIGNAL IO7L_ipd         : std_ulogic := 'U';
    SIGNAL IO8L_ipd         : std_ulogic := 'U';
    SIGNAL IO9L_ipd         : std_ulogic := 'U';
    SIGNAL IO10L_ipd        : std_ulogic := 'U';
    SIGNAL IO11L_ipd        : std_ulogic := 'U';
    SIGNAL IO12L_ipd        : std_ulogic := 'U';
    SIGNAL IO13L_ipd        : std_ulogic := 'U';
    SIGNAL IO14L_ipd        : std_ulogic := 'U';
    SIGNAL IO15L_ipd        : std_ulogic := 'U';
    SIGNAL IO16L_ipd        : std_ulogic := 'U';
    SIGNAL IO17L_ipd        : std_ulogic := 'U';
    SIGNAL IO18L_ipd        : std_ulogic := 'U';
    SIGNAL IO19L_ipd        : std_ulogic := 'U';
    SIGNAL IO20L_ipd        : std_ulogic := 'U';
    SIGNAL IO21L_ipd        : std_ulogic := 'U';
    SIGNAL IO22L_ipd        : std_ulogic := 'U';
    SIGNAL IO23L_ipd        : std_ulogic := 'U';
    SIGNAL IO24L_ipd        : std_ulogic := 'U';
    SIGNAL IO25L_ipd        : std_ulogic := 'U';
    SIGNAL IO26L_ipd        : std_ulogic := 'U';
    SIGNAL IO27L_ipd        : std_ulogic := 'U';
    SIGNAL IO28L_ipd        : std_ulogic := 'U';
    SIGNAL IO29L_ipd        : std_ulogic := 'U';
    SIGNAL IO30L_ipd        : std_ulogic := 'U';
    SIGNAL IO31L_ipd        : std_ulogic := 'U';
    SIGNAL IO32L_ipd        : std_ulogic := 'U';
    SIGNAL IO33L_ipd        : std_ulogic := 'U';
    SIGNAL IO34L_ipd        : std_ulogic := 'U';
    SIGNAL IO35L_ipd        : std_ulogic := 'U';
    --Left port control
    SIGNAL CE0NegL_ipd      : std_ulogic := 'U';
    SIGNAL CE1L_ipd         : std_ulogic := 'U';
    SIGNAL OENegL_ipd       : std_ulogic := 'U';
    SIGNAL RWL_ipd          : std_ulogic := 'U';
    SIGNAL CLKL_ipd         : std_ulogic := 'U';
    SIGNAL PLNegL_ipd       : std_ulogic := 'U';
    SIGNAL ADSNegL_ipd      : std_ulogic := 'U';
    SIGNAL CNTENNegL_ipd    : std_ulogic := 'U';
    SIGNAL REPEATNegL_ipd   : std_ulogic := 'U';
    SIGNAL BE0NegL_ipd      : std_ulogic := 'U';
    SIGNAL BE1NegL_ipd      : std_ulogic := 'U';
    SIGNAL BE2NegL_ipd      : std_ulogic := 'U';
    SIGNAL BE3NegL_ipd      : std_ulogic := 'U';
    SIGNAL ZZL_ipd          : std_ulogic := 'U';

    --Right port Address lines
    SIGNAL A0R_ipd          : std_ulogic := 'U';
    SIGNAL A1R_ipd          : std_ulogic := 'U';
    SIGNAL A2R_ipd          : std_ulogic := 'U';
    SIGNAL A3R_ipd          : std_ulogic := 'U';
    SIGNAL A4R_ipd          : std_ulogic := 'U';
    SIGNAL A5R_ipd          : std_ulogic := 'U';
    SIGNAL A6R_ipd          : std_ulogic := 'U';
    SIGNAL A7R_ipd          : std_ulogic := 'U';
    SIGNAL A8R_ipd          : std_ulogic := 'U';
    SIGNAL A9R_ipd          : std_ulogic := 'U';
    SIGNAL A10R_ipd         : std_ulogic := 'U';
    SIGNAL A11R_ipd         : std_ulogic := 'U';
    SIGNAL A12R_ipd         : std_ulogic := 'U';
    SIGNAL A13R_ipd         : std_ulogic := 'U';
    SIGNAL A14R_ipd         : std_ulogic := 'U';
    SIGNAL A15R_ipd         : std_ulogic := 'U';
    --Right port IO lines
    SIGNAL IO0R_ipd         : std_ulogic := 'U';
    SIGNAL IO1R_ipd         : std_ulogic := 'U';
    SIGNAL IO2R_ipd         : std_ulogic := 'U';
    SIGNAL IO3R_ipd         : std_ulogic := 'U';
    SIGNAL IO4R_ipd         : std_ulogic := 'U';
    SIGNAL IO5R_ipd         : std_ulogic := 'U';
    SIGNAL IO6R_ipd         : std_ulogic := 'U';
    SIGNAL IO7R_ipd         : std_ulogic := 'U';
    SIGNAL IO8R_ipd         : std_ulogic := 'U';
    SIGNAL IO9R_ipd         : std_ulogic := 'U';
    SIGNAL IO10R_ipd        : std_ulogic := 'U';
    SIGNAL IO11R_ipd        : std_ulogic := 'U';
    SIGNAL IO12R_ipd        : std_ulogic := 'U';
    SIGNAL IO13R_ipd        : std_ulogic := 'U';
    SIGNAL IO14R_ipd        : std_ulogic := 'U';
    SIGNAL IO15R_ipd        : std_ulogic := 'U';
    SIGNAL IO16R_ipd        : std_ulogic := 'U';
    SIGNAL IO17R_ipd        : std_ulogic := 'U';
    SIGNAL IO18R_ipd        : std_ulogic := 'U';
    SIGNAL IO19R_ipd        : std_ulogic := 'U';
    SIGNAL IO20R_ipd        : std_ulogic := 'U';
    SIGNAL IO21R_ipd        : std_ulogic := 'U';
    SIGNAL IO22R_ipd        : std_ulogic := 'U';
    SIGNAL IO23R_ipd        : std_ulogic := 'U';
    SIGNAL IO24R_ipd        : std_ulogic := 'U';
    SIGNAL IO25R_ipd        : std_ulogic := 'U';
    SIGNAL IO26R_ipd        : std_ulogic := 'U';
    SIGNAL IO27R_ipd        : std_ulogic := 'U';
    SIGNAL IO28R_ipd        : std_ulogic := 'U';
    SIGNAL IO29R_ipd        : std_ulogic := 'U';
    SIGNAL IO30R_ipd        : std_ulogic := 'U';
    SIGNAL IO31R_ipd        : std_ulogic := 'U';
    SIGNAL IO32R_ipd        : std_ulogic := 'U';
    SIGNAL IO33R_ipd        : std_ulogic := 'U';
    SIGNAL IO34R_ipd        : std_ulogic := 'U';
    SIGNAL IO35R_ipd        : std_ulogic := 'U';
     --Right port controml lines
    SIGNAL CE0NegR_ipd      : std_ulogic := 'U';
    SIGNAL CE1R_ipd         : std_ulogic := 'U';
    SIGNAL OENegR_ipd       : std_ulogic := 'U';
    SIGNAL RWR_ipd          : std_ulogic := 'U';
    SIGNAL CLKR_ipd         : std_ulogic := 'U';
    SIGNAL PLNegR_ipd       : std_ulogic := 'U';
    SIGNAL ADSNegR_ipd      : std_ulogic := 'U';
    SIGNAL CNTENNegR_ipd    : std_ulogic := 'U';
    SIGNAL REPEATNegR_ipd   : std_ulogic := 'U';
    SIGNAL BE0NegR_ipd      : std_ulogic := 'U';
    SIGNAL BE1NegR_ipd      : std_ulogic := 'U';
    SIGNAL BE2NegR_ipd      : std_ulogic := 'U';