idt70t3589dr.vhd

vhdl cod for ram.For sp3e

-------------------------------------------------------------------------------
--  File Name: idt70t3589dr.vhd
-------------------------------------------------------------------------------
--  Copyright (C) 2003-2008 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-------------------------------------------------------------------------------
--
--  MODIFICATION HISTORY:
--
--  version: |  author:        | mod date: | changes made:
--    V1.0     M.Marinkovic     03 Oct 09   Inital Release
--    V1.1     R. Munden        04 Mar 29   made counter independent of CEs
--                                          corrected setup/hold checks
--    V1.2     R. Munden        04 Nov 14   corrected output enable behavior
--    V1.3     R. Munden        05 Aug 06   correct right port PL read
--    V1.4     R. Munden        08 Jul 03   corrected VITAL generic names
--
-------------------------------------------------------------------------------
--  PART DESCRIPTION:
--
--  Library:    RAM
--  Technology:
--  Part:        IDT70T3589DR
--
--   Description: 64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM PQFP package
-------------------------------------------------------------------------------

LIBRARY IEEE;
    USE IEEE.std_logic_1164.ALL;
    USE IEEE.vital_timing.ALL;
    USE IEEE.vital_primitives.ALL;
    USE STD.textio.ALL;

LIBRARY FMF;
    USE FMF.gen_utils.ALL;
    USE FMF.conversions.ALL;

-------------------------------------------------------------------------------
-- ENTITY DECLARATION
-------------------------------------------------------------------------------
ENTITY idt70t3589dr IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_A0L            : VitalDelayType01  := VitalZeroDelay01;
        tipd_A1L            : VitalDelayType01  := VitalZeroDelay01;
        tipd_A2L            : VitalDelayType01  := VitalZeroDelay01;
        tipd_A3L            : VitalDelayType01  := VitalZeroDelay01;
        tipd_A4L            : VitalDelayType01  := VitalZeroDelay01;
        tipd_A5L            : VitalDelayType01  := VitalZeroDelay01;
        tipd_A6L            : VitalDelayType01  := VitalZeroDelay01;
        tipd_A7L            : VitalDelayType01  := VitalZeroDelay01;
        tipd_A8L            : VitalDelayType01  := VitalZeroDelay01;
        tipd_A9L            : VitalDelayType01  := VitalZeroDelay01;
        tipd_A10L           : VitalDelayType01  := VitalZeroDelay01;
        tipd_A11L           : VitalDelayType01  := VitalZeroDelay01;
        tipd_A12L           : VitalDelayType01  := VitalZeroDelay01;
        tipd_A13L           : VitalDelayType01  := VitalZeroDelay01;
        tipd_A14L           : VitalDelayType01  := VitalZeroDelay01;
        tipd_A15L           : VitalDelayType01  := VitalZeroDelay01;

        tipd_IO0L           : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO1L           : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO2L           : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO3L           : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO4L           : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO5L           : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO6L           : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO7L           : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO8L           : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO9L           : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO10L          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO11L          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO12L          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO13L          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO14L          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO15L          : VitalDelayType01z := VitalZeroDelay01Z;
        tipd_IO16L          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO17L          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO18L          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO19L          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO20L          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO21L          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO22L          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO23L          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO24L          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO25L          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO26L          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO27L          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO28L          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO29L          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO30L          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO31L          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO32L          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO33L          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO34L          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO35L          : VitalDelayType01Z := VitalZeroDelay01Z;

        tipd_CE0NegL        : VitalDelayType01  := VitalZeroDelay01;
        tipd_CE1L           : VitalDelayType01  := VitalZeroDelay01;
        tipd_RWL            : VitalDelayType01  := VitalZeroDelay01;
        tipd_CLKL           : VitalDelayType01  := VitalZeroDelay01;
        tipd_ADSNegL        : VitalDelayType01  := VitalZeroDelay01;
        tipd_CNTENNegL      : VitalDelayType01  := VitalZeroDelay01;
        tipd_REPEATNegL     : VitalDelayType01  := VitalZeroDelay01;
        tipd_BE0NegL        : VitalDelayType01  := VitalZeroDelay01;
        tipd_BE1NegL        : VitalDelayType01  := VitalZeroDelay01;
        tipd_BE2NegL        : VitalDelayType01  := VitalZeroDelay01;
        tipd_BE3NegL        : VitalDelayType01  := VitalZeroDelay01;
        tipd_ZZL            : VitalDelayType01  := VitalZeroDelay01;

        tipd_A0R            : VitalDelayType01  := VitalZeroDelay01;
        tipd_A1R            : VitalDelayType01  := VitalZeroDelay01;
        tipd_A2R            : VitalDelayType01  := VitalZeroDelay01;
        tipd_A3R            : VitalDelayType01  := VitalZeroDelay01;
        tipd_A4R            : VitalDelayType01  := VitalZeroDelay01;
        tipd_A5R            : VitalDelayType01  := VitalZeroDelay01;
        tipd_A6R            : VitalDelayType01  := VitalZeroDelay01;
        tipd_A7R            : VitalDelayType01  := VitalZeroDelay01;
        tipd_A8R            : VitalDelayType01  := VitalZeroDelay01;
        tipd_A9R            : VitalDelayType01  := VitalZeroDelay01;
        tipd_A10R           : VitalDelayType01  := VitalZeroDelay01;
        tipd_A11R           : VitalDelayType01  := VitalZeroDelay01;
        tipd_A12R           : VitalDelayType01  := VitalZeroDelay01;
        tipd_A13R           : VitalDelayType01  := VitalZeroDelay01;
        tipd_A14R           : VitalDelayType01  := VitalZeroDelay01;
        tipd_A15R           : VitalDelayType01  := VitalZeroDelay01;

        tipd_IO0R           : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO1R           : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO2R           : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO3R           : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO4R           : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO5R           : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO6R           : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO7R           : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO8R           : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO9R           : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO10R          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO11R          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO12R          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO13R          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO14R          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO15R          : VitalDelayType01z := VitalZeroDelay01Z;
        tipd_IO16R          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO17R          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO18R          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO19R          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO20R          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO21R          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO22R          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO23R          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO24R          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO25R          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO26R          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO27R          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO28R          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO29R          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO30R          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO31R          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO32R          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO33R          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO34R          : VitalDelayType01Z := VitalZeroDelay01Z;
        tipd_IO35R          : VitalDelayType01Z := VitalZeroDelay01Z;

        tipd_CE0NegR        : VitalDelayType01  := VitalZeroDelay01;
        tipd_CE1R           : VitalDelayType01  := VitalZeroDelay01;
        tipd_RWR            : VitalDelayType01  := VitalZeroDelay01;
        tipd_CLKR           : VitalDelayType01  := VitalZeroDelay01;
        tipd_ADSNegR        : VitalDelayType01  := VitalZeroDelay01;
        tipd_CNTENNegR      : VitalDelayType01  := VitalZeroDelay01;
        tipd_REPEATNegR     : VitalDelayType01  := VitalZeroDelay01;
        tipd_BE0NegR        : VitalDelayType01  := VitalZeroDelay01;
        tipd_BE1NegR        : VitalDelayType01  := VitalZeroDelay01;
        tipd_BE2NegR        : VitalDelayType01  := VitalZeroDelay01;
        tipd_BE3NegR        : VitalDelayType01  := VitalZeroDelay01;
        tipd_ZZR            : VitalDelayType01  := VitalZeroDelay01;

        tipd_OENegL         : VitalDelayType01  := VitalZeroDelay01;
        tipd_OENegR         : VitalDelayType01  := VitalZeroDelay01;
        tipd_PLNegL         : VitalDelayType01  := VitalZeroDelay01;
        tipd_PLNegR         : VitalDelayType01  := VitalZeroDelay01;

        -- tpd delays
        tpd_CLKL_COLNegL      : VitalDelayType01  := UnitDelay01;  --tCOLR,tCOLS
        tpd_CLKL_IntNegL      : VitalDelayType01  := UnitDelay01;  --tINR,tINS
        -- (tCD2,tCD2, tCKHZ,tCKHZ, tCKHZ, tCKHZ)
        tpd_CLKL_IO0L         : VitalDelayType01Z := UnitDelay01Z;
        -- (tCD1,tCD1, tCKHZ,tCKHZ, tCKHZ, tCKHZ)
        tpd_CLKR_IO0R         : VitalDelayType01Z := UnitDelay01Z;
        -- (tOE, tOE, tOHz, tOHZ, tOHZ, tOHZ)
        tpd_OENegL_IO0L        : VitalDelayType01Z := UnitDelay01Z;
        -- tpw values: pulse widths
        --pipeline mode
        tpw_CLKL_posedge     : VitalDelayType    := UnitDelay; --tCH2
        tpw_CLKL_negedge     : VitalDelayType    := UnitDelay; --tCL2
        --flowthrough
        tpw_CLKR_posedge     : VitalDelayType    := UnitDelay; --tCH1
        tpw_CLKR_negedge     : VitalDelayType    := UnitDelay; --tCL1
        --tck
        -- tperiod min (calculated as 1/max freq)
        --pipeline
        tperiod_CLKL         : VitalDelayType    := UnitDelay; --tCYC2
        --flowthrough
        tperiod_CLKR         : VitalDelayType    := UnitDelay; --tCYC1
        -- tsetup values: setup times
        --tSA, tSC, tSB, tSW, tSD, tSAD, tSCN, tSRPT
        tsetup_A0L_CLKL        : VitalDelayType := UnitDelay;
        -- thold values: hold times
        --tHA, tHC, tHB, tHW, tHD, tHAD, tHCN, tHRPT
        thold_A0L_CLKL         : VitalDelayType := UnitDelay;
        --t device values
        tdevice_TCO         : VitalDelayType    := 5 ns; --tCO

        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        SeverityMode        : SEVERITY_LEVEL := WARNING;
        -- memory file to be loaded
        mem_file_name       : STRING    := "none";
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        --Left port Address lines
        A0L              : IN    std_logic := 'U';
        A1L              : IN    std_logic := 'U';
        A2L              : IN    std_logic := 'U';
        A3L              : IN    std_logic := 'U';
        A4L              : IN    std_logic := 'U';
        A5L              : IN    std_logic := 'U';
        A6L              : IN    std_logic := 'U';
        A7L              : IN    std_logic := 'U';
        A8L              : IN    std_logic := 'U';
        A9L              : IN    std_logic := 'U';
        A10L             : IN    std_logic := 'U';
        A11L             : IN    std_logic := 'U';
        A12L             : IN    std_logic := 'U';
        A13L             : IN    std_logic := 'U';
        A14L             : IN    std_logic := 'U';
        A15L             : IN    std_logic := 'U';
        --Left port IO lines
        IO0L             : INOUT    std_logic := 'U';
        IO1L             : INOUT    std_logic := 'U';
        IO2L             : INOUT    std_logic := 'U';
        IO3L             : INOUT    std_logic := 'U';
        IO4L             : INOUT    std_logic := 'U';
        IO5L             : INOUT    std_logic := 'U';
        IO6L             : INOUT    std_logic := 'U';
        IO7L             : INOUT    std_logic := 'U';
        IO8L             : INOUT    std_logic := 'U';
        IO9L             : INOUT    std_logic := 'U';
        IO10L            : INOUT    std_logic := 'U';
        IO11L            : INOUT    std_logic := 'U';
        IO12L            : INOUT    std_logic := 'U';
        IO13L            : INOUT    std_logic := 'U';
        IO14L            : INOUT    std_logic := 'U';
        IO15L            : INOUT    std_logic := 'U';
        IO16L            : INOUT    std_logic := 'U';