mb811643242.vhd

vhdl cod for ram.For sp3e

    SIGNAL DQ12_nwv            : UX01 := 'X';
    SIGNAL DQ13_nwv            : UX01 := 'X';
    SIGNAL DQ14_nwv            : UX01 := 'X';
    SIGNAL DQ15_nwv            : UX01 := 'X';
    SIGNAL DQ16_nwv            : UX01 := 'X';
    SIGNAL DQ17_nwv            : UX01 := 'X';
    SIGNAL DQ18_nwv            : UX01 := 'X';
    SIGNAL DQ19_nwv            : UX01 := 'X';
    SIGNAL DQ20_nwv            : UX01 := 'X';
    SIGNAL DQ21_nwv            : UX01 := 'X';
    SIGNAL DQ22_nwv            : UX01 := 'X';
    SIGNAL DQ23_nwv            : UX01 := 'X';
    SIGNAL DQ24_nwv            : UX01 := 'X';
    SIGNAL DQ25_nwv            : UX01 := 'X';
    SIGNAL DQ26_nwv            : UX01 := 'X';
    SIGNAL DQ27_nwv            : UX01 := 'X';
    SIGNAL DQ28_nwv            : UX01 := 'X';
    SIGNAL DQ29_nwv            : UX01 := 'X';
    SIGNAL DQ30_nwv            : UX01 := 'X';
    SIGNAL DQ31_nwv            : UX01 := 'X';
    SIGNAL A0_nwv              : UX01 := 'X';
    SIGNAL A1_nwv              : UX01 := 'X';
    SIGNAL A2_nwv              : UX01 := 'X';
    SIGNAL A3_nwv              : UX01 := 'X';
    SIGNAL A4_nwv              : UX01 := 'X';
    SIGNAL A5_nwv              : UX01 := 'X';
    SIGNAL A6_nwv              : UX01 := 'X';
    SIGNAL A7_nwv              : UX01 := 'X';
    SIGNAL A8_nwv              : UX01 := 'X';
    SIGNAL A9_nwv              : UX01 := 'X';
    SIGNAL A10_nwv             : UX01 := 'X';
    SIGNAL CLK_nwv             : std_ulogic := 'U';
    SIGNAL CKE_nwv             : std_ulogic := 'U';
    SIGNAL WENeg_nwv           : std_ulogic := 'U';
    SIGNAL RASNeg_nwv          : std_ulogic := 'U';
    SIGNAL CSNeg_nwv           : std_ulogic := 'U';
    SIGNAL CASNeg_nwv          : std_ulogic := 'U';

    SIGNAL rct_in            : std_ulogic := '0';
    SIGNAL rct_out           : std_ulogic := '0';
    SIGNAL rcdt_in           : std_ulogic_vector(3 downto 0) := (others => '0');
    SIGNAL rcdt_out          : std_ulogic_vector(3 downto 0) := (others => '0');
    SIGNAL pre_in            : std_ulogic := '0';
    SIGNAL pre_out           : std_ulogic := '0';
    SIGNAL refreshed_in      : std_ulogic := '0';
    SIGNAL refreshed_out     : std_ulogic := '0';
    SIGNAL rcar_out          : std_ulogic := '0';
    SIGNAL rcar_in           : std_ulogic := '0';
    SIGNAL wrt_in            : std_ulogic := '0';
    SIGNAL wrt_out           : std_ulogic := '0';
    SIGNAL ras_in            : std_ulogic_vector(3 downto 0) := (others => '0');
    SIGNAL ras_out           : std_ulogic_vector(3 downto 0) := (others => '0');

BEGIN

    ----------------------------------------------------------------------------
    -- Internal Delays
    ----------------------------------------------------------------------------
    -- Artificial VITAL primitives to incorporate internal delays
    REF : VitalBuf (refreshed_out, refreshed_in, (UnitDelay, tdevice_REF));
    TRC : VitalBuf (rct_out, rct_in, (tdevice_TRC, UnitDelay));
    TRCD : VitalBuf (rcdt_out(0), rcdt_in(0), (UnitDelay, tdevice_TRCD));
    TRCD1 : VitalBuf (rcdt_out(1), rcdt_in(1), (UnitDelay, tdevice_TRCD));
    TRCD2 : VitalBuf (rcdt_out(2), rcdt_in(2), (UnitDelay, tdevice_TRCD));
    TRCD3 : VitalBuf (rcdt_out(3), rcdt_in(3), (UnitDelay, tdevice_TRCD));
    TRP : VitalBuf (pre_out, pre_in, (tdevice_TRP, UnitDelay));
    TRCAR : VitalBuf (rcar_out, rcar_in, (tdevice_TRCAR, UnitDelay));
    TWR : VitalBuf (wrt_out, wrt_in, (UnitDelay, tdevice_TWR));
    TRAS : VitalBuf (ras_out(0), ras_in(0), tdevice_TRAS);
    TRAS1 : VitalBuf (ras_out(1), ras_in(1), tdevice_TRAS);
    TRAS2 : VitalBuf (ras_out(2), ras_in(2), tdevice_TRAS);
    TRAS3 : VitalBuf (ras_out(3), ras_in(3), tdevice_TRAS);

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (BA0_ipd, BA0, tipd_BA0);
        w_2 : VitalWireDelay (BA1_ipd, BA1, tipd_BA1);
        w_3 : VitalWireDelay (DQM0_ipd, DQM0, tipd_DQM0);
        w_4 : VitalWireDelay (DQM1_ipd, DQM1, tipd_DQM1);
        w_5 : VitalWireDelay (DQM2_ipd, DQM2, tipd_DQM2);
        w_6 : VitalWireDelay (DQM3_ipd, DQM3, tipd_DQM3);
        w_7 : VitalWireDelay (DQ0_ipd, DQ0, tipd_DQ0);
        w_8 : VitalWireDelay (DQ1_ipd, DQ1, tipd_DQ1);
        w_9 : VitalWireDelay (DQ2_ipd, DQ2, tipd_DQ2);
        w_10 : VitalWireDelay (DQ3_ipd, DQ3, tipd_DQ3);
        w_11 : VitalWireDelay (DQ4_ipd, DQ4, tipd_DQ4);
        w_12 : VitalWireDelay (DQ5_ipd, DQ5, tipd_DQ5);
        w_13 : VitalWireDelay (DQ6_ipd, DQ6, tipd_DQ6);
        w_14 : VitalWireDelay (DQ7_ipd, DQ7, tipd_DQ7);
        w_15 : VitalWireDelay (DQ8_ipd, DQ8, tipd_DQ8);
        w_16 : VitalWireDelay (DQ9_ipd, DQ9, tipd_DQ9);
        w_17 : VitalWireDelay (DQ10_ipd, DQ10, tipd_DQ10);
        w_18 : VitalWireDelay (DQ11_ipd, DQ11, tipd_DQ11);
        w_19 : VitalWireDelay (DQ12_ipd, DQ12, tipd_DQ12);
        w_20 : VitalWireDelay (DQ13_ipd, DQ13, tipd_DQ13);
        w_21 : VitalWireDelay (DQ14_ipd, DQ14, tipd_DQ14);
        w_22 : VitalWireDelay (DQ15_ipd, DQ15, tipd_DQ15);
        w_23 : VitalWireDelay (DQ16_ipd, DQ16, tipd_DQ16);
        w_24 : VitalWireDelay (DQ17_ipd, DQ17, tipd_DQ17);
        w_25 : VitalWireDelay (DQ18_ipd, DQ18, tipd_DQ18);
        w_26 : VitalWireDelay (DQ19_ipd, DQ19, tipd_DQ19);
        w_27 : VitalWireDelay (DQ20_ipd, DQ20, tipd_DQ20);
        w_28 : VitalWireDelay (DQ21_ipd, DQ21, tipd_DQ21);
        w_29 : VitalWireDelay (DQ22_ipd, DQ22, tipd_DQ22);
        w_30 : VitalWireDelay (DQ23_ipd, DQ23, tipd_DQ23);
        w_31 : VitalWireDelay (DQ24_ipd, DQ24, tipd_DQ24);
        w_32 : VitalWireDelay (DQ25_ipd, DQ25, tipd_DQ25);
        w_33 : VitalWireDelay (DQ26_ipd, DQ26, tipd_DQ26);
        w_34 : VitalWireDelay (DQ27_ipd, DQ27, tipd_DQ27);
        w_35 : VitalWireDelay (DQ28_ipd, DQ28, tipd_DQ28);
        w_36 : VitalWireDelay (DQ29_ipd, DQ29, tipd_DQ29);
        w_37 : VitalWireDelay (DQ30_ipd, DQ30, tipd_DQ30);
        w_38 : VitalWireDelay (DQ31_ipd, DQ31, tipd_DQ31);
        w_39 : VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
        w_40 : VitalWireDelay (CKE_ipd, CKE, tipd_CKE);
        w_41 : VitalWireDelay (A0_ipd, A0, tipd_A0);
        w_42 : VitalWireDelay (A1_ipd, A1, tipd_A1);
        w_43 : VitalWireDelay (A2_ipd, A2, tipd_A2);
        w_44 : VitalWireDelay (A3_ipd, A3, tipd_A3);
        w_45 : VitalWireDelay (A4_ipd, A4, tipd_A4);
        w_46 : VitalWireDelay (A5_ipd, A5, tipd_A5);
        w_47 : VitalWireDelay (A6_ipd, A6, tipd_A6);
        w_48 : VitalWireDelay (A7_ipd, A7, tipd_A7);
        w_49 : VitalWireDelay (A8_ipd, A8, tipd_A8);
        w_50 : VitalWireDelay (A9_ipd, A9, tipd_A9);
        w_51 : VitalWireDelay (A10_ipd, A10, tipd_A10);
        w_52 : VitalWireDelay (WENeg_ipd, WENeg, tipd_WENeg);
        w_53 : VitalWireDelay (RASNeg_ipd, RASNeg, tipd_RASNeg);
        w_54 : VitalWireDelay (CSNeg_ipd, CSNeg, tipd_CSNeg);
        w_55 : VitalWireDelay (CASNeg_ipd, CASNeg, tipd_CASNeg);

    END BLOCK;

    WENeg_nwv <= To_UX01(WENeg_ipd);
    RASNeg_nwv <= To_UX01(RASNeg_ipd);
    CSNeg_nwv <= To_UX01(CSNeg_ipd);
    CASNeg_nwv <= To_UX01(CASNeg_ipd);
    CLK_nwv <= To_UX01(CLK_ipd);
    CKE_nwv <= To_UX01(CKE_ipd);
    BA0_nwv <= To_UX01(BA0_ipd);
    BA1_nwv <= To_UX01(BA1_ipd);
    DQM0_nwv <= To_UX01(DQM0_ipd);
    DQM1_nwv <= To_UX01(DQM1_ipd);
    DQM2_nwv <= To_UX01(DQM2_ipd);
    DQM3_nwv <= To_UX01(DQM3_ipd);
    DQ0_nwv <= To_UX01(DQ0_ipd);
    DQ1_nwv <= To_UX01(DQ1_ipd);
    DQ2_nwv <= To_UX01(DQ2_ipd);
    DQ3_nwv <= To_UX01(DQ3_ipd);
    DQ4_nwv <= To_UX01(DQ4_ipd);
    DQ5_nwv <= To_UX01(DQ5_ipd);
    DQ6_nwv <= To_UX01(DQ6_ipd);
    DQ7_nwv <= To_UX01(DQ7_ipd);
    DQ8_nwv <= To_UX01(DQ8_ipd);
    DQ9_nwv <= To_UX01(DQ9_ipd);
    DQ10_nwv <= To_UX01(DQ10_ipd);
    DQ11_nwv <= To_UX01(DQ11_ipd);
    DQ12_nwv <= To_UX01(DQ12_ipd);
    DQ13_nwv <= To_UX01(DQ13_ipd);
    DQ14_nwv <= To_UX01(DQ14_ipd);
    DQ15_nwv <= To_UX01(DQ15_ipd);
    DQ16_nwv <= To_UX01(DQ16_ipd);
    DQ17_nwv <= To_UX01(DQ17_ipd);
    DQ18_nwv <= To_UX01(DQ18_ipd);
    DQ19_nwv <= To_UX01(DQ19_ipd);
    DQ20_nwv <= To_UX01(DQ20_ipd);
    DQ21_nwv <= To_UX01(DQ21_ipd);
    DQ22_nwv <= To_UX01(DQ22_ipd);
    DQ23_nwv <= To_UX01(DQ23_ipd);
    DQ24_nwv <= To_UX01(DQ24_ipd);
    DQ25_nwv <= To_UX01(DQ25_ipd);
    DQ26_nwv <= To_UX01(DQ26_ipd);
    DQ27_nwv <= To_UX01(DQ27_ipd);
    DQ28_nwv <= To_UX01(DQ28_ipd);
    DQ29_nwv <= To_UX01(DQ29_ipd);
    DQ30_nwv <= To_UX01(DQ30_ipd);
    DQ31_nwv <= To_UX01(DQ31_ipd);
    A0_nwv <= To_UX01(A0_ipd);
    A1_nwv <= To_UX01(A1_ipd);
    A2_nwv <= To_UX01(A2_ipd);
    A3_nwv <= To_UX01(A3_ipd);
    A4_nwv <= To_UX01(A4_ipd);
    A5_nwv <= To_UX01(A5_ipd);
    A6_nwv <= To_UX01(A6_ipd);
    A7_nwv <= To_UX01(A7_ipd);
    A8_nwv <= To_UX01(A8_ipd);
    A9_nwv <= To_UX01(A9_ipd);
    A10_nwv <= To_UX01(A10_ipd);

    ----------------------------------------------------------------------------
    -- Main Behavior Block
    ----------------------------------------------------------------------------
    Main : BLOCK

        PORT (
            BAIn            : IN    std_logic_vector(1 downto 0);
            DQM0In          : IN    std_ulogic := 'X';
            DQM1In          : IN    std_ulogic := 'X';
            DQM2In          : IN    std_ulogic := 'X';
            DQM3In          : IN    std_ulogic := 'X';
            DataIn          : IN    std_logic_vector(31 downto 0);
            DataOut         : OUT   std_logic_vector(31 downto 0)
                                                     := (others => 'Z');
            CLKIn           : IN    std_ulogic := 'X';
            CKEIn           : IN    std_ulogic := 'X';
            AddressIn       : IN    std_logic_vector(10 downto 0);
            WENegIn         : IN    std_ulogic := 'X';
            RASNegIn        : IN    std_ulogic := 'X';
            CSNegIn         : IN    std_ulogic := 'X';
            CASNegIn        : IN    std_ulogic := 'X'
        );
        PORT MAP (
            BAIn(0) => BA0_nwv,
            BAIn(1) => BA1_nwv,
            DQM0In => DQM0_nwv,
            DQM1In => DQM1_nwv,
            DQM2In => DQM2_nwv,
            DQM3In => DQM3_nwv,
            DataOut(0) =>  DQ0,
            DataOut(1) =>  DQ1,
            DataOut(2) =>  DQ2,
            DataOut(3) =>  DQ3,
            DataOut(4) =>  DQ4,
            DataOut(5) =>  DQ5,
            DataOut(6) =>  DQ6,
            DataOut(7) =>  DQ7,
            DataOut(8) =>  DQ8,
            DataOut(9) =>  DQ9,
            DataOut(10) =>  DQ10,
            DataOut(11) =>  DQ11,
            DataOut(12) =>  DQ12,
            DataOut(13) =>  DQ13,
            DataOut(14) =>  DQ14,
            DataOut(15) =>  DQ15,
            DataOut(16) =>  DQ16,
            DataOut(17) =>  DQ17,
            DataOut(18) =>  DQ18,
            DataOut(19) =>  DQ19,
            DataOut(20) =>  DQ20,
            DataOut(21) =>  DQ21,
            DataOut(22) =>  DQ22,
            DataOut(23) =>  DQ23,
            DataOut(24) =>  DQ24,
            DataOut(25) =>  DQ25,
            DataOut(26) =>  DQ26,
            DataOut(27) =>  DQ27,
            DataOut(28) =>  DQ28,
            DataOut(29) =>  DQ29,
            DataOut(30) =>  DQ30,
            DataOut(31) =>  DQ31,
            DataIn(0) =>  DQ0_nwv,
            DataIn(1) =>  DQ1_nwv,
            DataIn(2) =>  DQ2_nwv,
            DataIn(3) =>  DQ3_nwv,
            DataIn(4) =>  DQ4_nwv,
            DataIn(5) =>  DQ5_nwv,
            DataIn(6) =>  DQ6_nwv,
            DataIn(7) =>  DQ7_nwv,
            DataIn(8) =>  DQ8_nwv,
            DataIn(9) =>  DQ9_nwv,
            DataIn(10) =>  DQ10_nwv,
            DataIn(11) =>  DQ11_nwv,
            DataIn(12) =>  DQ12_nwv,
            DataIn(13) =>  DQ13_nwv,
            DataIn(14) =>  DQ14_nwv,
            DataIn(15) =>  DQ15_nwv,
            DataIn(16) =>  DQ16_nwv,
            DataIn(17) =>  DQ17_nwv,
            DataIn(18) =>  DQ18_nwv,
            DataIn(19) =>  DQ19_nwv,
            DataIn(20) =>  DQ20_nwv,
            DataIn(21) =>  DQ21_nwv,
            DataIn(22) =>  DQ22_nwv,
            DataIn(23) =>  DQ23_nwv,
            DataIn(24) =>  DQ24_nwv,
            DataIn(25) =>  DQ25_nwv,
            DataIn(26) =>  DQ26_nwv,