mb811643242.vhd

vhdl cod for ram.For sp3e

--------------------------------------------------------------------------------
--  File Name: mb811643242.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1999-2003 Free Model Foundry; http://www.FreeModelFoundry.com
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0    R. Munden    99 JUL 26   Initial coding
--    V2.0    R. Munden    99 NOV 06   rewrite based on km416s4030 V2.0
--    V2.1    R. Munden    00 JAN 22   Fixed corner case for write_suspend
--    V2.2    R. Munden   03 MAR 08    Changed type of some _nwv signals to
--                                     satisfy ncvhdl
--                                    
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:    RAM
--  Technology: LVTTL
--  Part:       KM432S2030, MB811643242
-- 
--  Description: 512K x 32Bit x 4 Banks SDRAM
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;
                USE FMF.conversions.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY mb811643242 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_BA0                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_BA1                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQM0                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQM1                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQM2                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQM3                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ0                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ1                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ2                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ3                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ4                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ5                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ6                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ7                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ8                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ9                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ10                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ11                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ12                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ13                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ14                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ15                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ16                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ17                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ18                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ19                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ20                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ21                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ22                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ23                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ24                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ25                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ26                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ27                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ28                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ29                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ30                : VitalDelayType01 := VitalZeroDelay01;
        tipd_DQ31                : VitalDelayType01 := VitalZeroDelay01;
        tipd_CLK                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_CKE                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_A0                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A1                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A2                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A3                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A4                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A5                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A6                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A7                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A8                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A9                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_A10                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_WENeg               : VitalDelayType01 := VitalZeroDelay01;
        tipd_RASNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_CSNeg               : VitalDelayType01 := VitalZeroDelay01;
        tipd_CASNeg              : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_CLK_DQ2              : VitalDelayType01Z := UnitDelay01Z;
        tpd_CLK_DQ3              : VitalDelayType01Z := UnitDelay01Z;
        -- tpw values: pulse widths
        tpw_CLK_posedge          : VitalDelayType    := UnitDelay;
        tpw_CLK_negedge          : VitalDelayType    := UnitDelay;
        -- tsetup values: setup times
        tsetup_DQ0_CLK           : VitalDelayType    := UnitDelay;
        -- thold values: hold times
        thold_DQ0_CLK            : VitalDelayType    := UnitDelay;
        -- tperiod_min: minimum clock period = 1/max freq
        tperiod_CLK_posedge      : VitalDelayType    := UnitDelay;
        -- tdevice values: values for internal delays
        -- time between refresh
        tdevice_REF              : VitalDelayType    := 15_625 ns;
        -- RAS cycle time
        tdevice_TRC              : VitalDelayType    := 90 ns;
        -- RAS to CAS delay time
        tdevice_TRCD             : VitalDelayType    := 30 ns;
        -- RAS precharge time
        tdevice_TRP              : VitalDelayType    := 30 ns;
        -- auto refresh
        tdevice_TRCAR            : VitalDelayType    := 90 ns;
        -- write recovery time
        tdevice_TWR              : VitalDelayType    := 15 ns;
        -- RAS active time
        tdevice_TRAS             : VitalDelayType01  := (60 ns, 120_000 ns);
        -- tpowerup: Power up initialization time. Data sheets say 100 us.
        -- May be shortened during simulation debug.
        tpowerup            : TIME      := 100 us;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        SeverityMode        : SEVERITY_LEVEL := WARNING;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        BA0             : IN    std_logic := 'U';
        BA1             : IN    std_logic := 'U';
        DQM0            : IN    std_logic := 'U';
        DQM1            : IN    std_logic := 'U';
        DQM2            : IN    std_logic := 'U';
        DQM3            : IN    std_logic := 'U';
        DQ0             : INOUT std_logic := 'U';
        DQ1             : INOUT std_logic := 'U';
        DQ2             : INOUT std_logic := 'U';
        DQ3             : INOUT std_logic := 'U';
        DQ4             : INOUT std_logic := 'U';
        DQ5             : INOUT std_logic := 'U';
        DQ6             : INOUT std_logic := 'U';
        DQ7             : INOUT std_logic := 'U';
        DQ8             : INOUT std_logic := 'U';
        DQ9             : INOUT std_logic := 'U';
        DQ10            : INOUT std_logic := 'U';
        DQ11            : INOUT std_logic := 'U';
        DQ12            : INOUT std_logic := 'U';
        DQ13            : INOUT std_logic := 'U';
        DQ14            : INOUT std_logic := 'U';
        DQ15            : INOUT std_logic := 'U';
        DQ16            : INOUT std_logic := 'U';
        DQ17            : INOUT std_logic := 'U';
        DQ18            : INOUT std_logic := 'U';
        DQ19            : INOUT std_logic := 'U';
        DQ20            : INOUT std_logic := 'U';
        DQ21            : INOUT std_logic := 'U';
        DQ22            : INOUT std_logic := 'U';
        DQ23            : INOUT std_logic := 'U';
        DQ24            : INOUT std_logic := 'U';
        DQ25            : INOUT std_logic := 'U';
        DQ26            : INOUT std_logic := 'U';
        DQ27            : INOUT std_logic := 'U';
        DQ28            : INOUT std_logic := 'U';
        DQ29            : INOUT std_logic := 'U';
        DQ30            : INOUT std_logic := 'U';
        DQ31            : INOUT std_logic := 'U';
        CLK             : IN    std_logic := 'U';
        CKE             : IN    std_logic := 'U';
        A0              : IN    std_logic := 'U';
        A1              : IN    std_logic := 'U';
        A2              : IN    std_logic := 'U';
        A3              : IN    std_logic := 'U';
        A4              : IN    std_logic := 'U';
        A5              : IN    std_logic := 'U';
        A6              : IN    std_logic := 'U';
        A7              : IN    std_logic := 'U';
        A8              : IN    std_logic := 'U';
        A9              : IN    std_logic := 'U';
        A10             : IN    std_logic := 'U';
        WENeg           : IN    std_logic := 'U';
        RASNeg          : IN    std_logic := 'U';
        CSNeg           : IN    std_logic := 'U';
        CASNeg          : IN    std_logic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of mb811643242 : ENTITY IS TRUE;
END mb811643242;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of mb811643242 IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT partID         : STRING := "mb811643242";
    CONSTANT hi_bank        : NATURAL := 3;
    CONSTANT depth          : NATURAL := 524287;

    SIGNAL CKEreg              : X01 := 'X';
    SIGNAL PoweredUp           : boolean := false;

    SIGNAL BA0_ipd             : std_ulogic := 'X';
    SIGNAL BA1_ipd             : std_ulogic := 'X';
    SIGNAL DQM0_ipd            : std_ulogic := 'X';
    SIGNAL DQM1_ipd            : std_ulogic := 'X';
    SIGNAL DQM2_ipd            : std_ulogic := 'X';
    SIGNAL DQM3_ipd            : std_ulogic := 'X';
    SIGNAL DQ0_ipd             : std_ulogic := 'X';
    SIGNAL DQ1_ipd             : std_ulogic := 'X';
    SIGNAL DQ2_ipd             : std_ulogic := 'X';
    SIGNAL DQ3_ipd             : std_ulogic := 'X';
    SIGNAL DQ4_ipd             : std_ulogic := 'X';
    SIGNAL DQ5_ipd             : std_ulogic := 'X';
    SIGNAL DQ6_ipd             : std_ulogic := 'X';
    SIGNAL DQ7_ipd             : std_ulogic := 'X';
    SIGNAL DQ8_ipd             : std_ulogic := 'X';
    SIGNAL DQ9_ipd             : std_ulogic := 'X';
    SIGNAL DQ10_ipd            : std_ulogic := 'X';
    SIGNAL DQ11_ipd            : std_ulogic := 'X';
    SIGNAL DQ12_ipd            : std_ulogic := 'X';
    SIGNAL DQ13_ipd            : std_ulogic := 'X';
    SIGNAL DQ14_ipd            : std_ulogic := 'X';
    SIGNAL DQ15_ipd            : std_ulogic := 'X';
    SIGNAL DQ16_ipd            : std_ulogic := 'X';
    SIGNAL DQ17_ipd            : std_ulogic := 'X';
    SIGNAL DQ18_ipd            : std_ulogic := 'X';
    SIGNAL DQ19_ipd            : std_ulogic := 'X';
    SIGNAL DQ20_ipd            : std_ulogic := 'X';
    SIGNAL DQ21_ipd            : std_ulogic := 'X';
    SIGNAL DQ22_ipd            : std_ulogic := 'X';
    SIGNAL DQ23_ipd            : std_ulogic := 'X';
    SIGNAL DQ24_ipd            : std_ulogic := 'X';
    SIGNAL DQ25_ipd            : std_ulogic := 'X';
    SIGNAL DQ26_ipd            : std_ulogic := 'X';
    SIGNAL DQ27_ipd            : std_ulogic := 'X';
    SIGNAL DQ28_ipd            : std_ulogic := 'X';
    SIGNAL DQ29_ipd            : std_ulogic := 'X';
    SIGNAL DQ30_ipd            : std_ulogic := 'X';
    SIGNAL DQ31_ipd            : std_ulogic := 'X';
    SIGNAL CLK_ipd             : std_ulogic := 'X';
    SIGNAL CKE_ipd             : std_ulogic := 'X';
    SIGNAL A0_ipd              : std_ulogic := 'X';
    SIGNAL A1_ipd              : std_ulogic := 'X';
    SIGNAL A2_ipd              : std_ulogic := 'X';
    SIGNAL A3_ipd              : std_ulogic := 'X';
    SIGNAL A4_ipd              : std_ulogic := 'X';
    SIGNAL A5_ipd              : std_ulogic := 'X';
    SIGNAL A6_ipd              : std_ulogic := 'X';
    SIGNAL A7_ipd              : std_ulogic := 'X';
    SIGNAL A8_ipd              : std_ulogic := 'X';
    SIGNAL A9_ipd              : std_ulogic := 'X';
    SIGNAL A10_ipd             : std_ulogic := 'X';
    SIGNAL WENeg_ipd           : std_ulogic := 'X';
    SIGNAL RASNeg_ipd          : std_ulogic := 'X';
    SIGNAL CSNeg_ipd           : std_ulogic := 'X';
    SIGNAL CASNeg_ipd          : std_ulogic := 'X';

    SIGNAL BA0_nwv             : std_ulogic := 'U';
    SIGNAL BA1_nwv             : std_ulogic := 'U';
    SIGNAL DQM0_nwv            : std_ulogic := 'U';
    SIGNAL DQM1_nwv            : std_ulogic := 'U';
    SIGNAL DQM2_nwv            : std_ulogic := 'U';
    SIGNAL DQM3_nwv            : std_ulogic := 'U';
    SIGNAL DQ0_nwv             : UX01 := 'X';
    SIGNAL DQ1_nwv             : UX01 := 'X';
    SIGNAL DQ2_nwv             : UX01 := 'X';
    SIGNAL DQ3_nwv             : UX01 := 'X';
    SIGNAL DQ4_nwv             : UX01 := 'X';
    SIGNAL DQ5_nwv             : UX01 := 'X';
    SIGNAL DQ6_nwv             : UX01 := 'X';
    SIGNAL DQ7_nwv             : UX01 := 'X';
    SIGNAL DQ8_nwv             : UX01 := 'X';
    SIGNAL DQ9_nwv             : UX01 := 'X';
    SIGNAL DQ10_nwv            : UX01 := 'X';
    SIGNAL DQ11_nwv            : UX01 := 'X';