xc18v04.vhd

vhdl cod for ram.For sp3e

            IF ESTART = '0' THEN
                EDONE <= '0';
            ELSE
                IF LongTiming THEN
                    EDONE <= '1' AFTER (tdevice_ERS - 1 ns);
                ELSE
                    EDONE <= '1' AFTER (tdevice_ERS/10000 - 1 ns);
                END IF;
            END IF;
        END PROCESS ErsTime;

    ---------------------------------------------------------------------------
    -- Main Behavior Process
    -- combinational process for next state generation
    ---------------------------------------------------------------------------
        StateGen_ISP :PROCESS(Instruct, EDONE, PDONE)

        BEGIN
        -----------------------------------------------------------------------
        -- Functionality Section
        -----------------------------------------------------------------------

            CASE current_state IS
                WHEN IDLE          =>
                    IF Instruct'EVENT AND Instruct = ispen THEN
                        next_state <= ISP_MODE;
                    ELSE
                        next_state <= IDLE;
                    END IF;

                WHEN ISP_MODE       =>
                    IF Instruct'EVENT AND Instruct = ferase AND ISP THEN
                        next_state <= ERASE;
                    ELSIF Instruct'EVENT AND Instruct = fpgm AND ISP THEN
                        next_state <= PROG;
                    ELSIF Instruct'EVENT AND Instruct = fdata3
                    AND ISP AND Address = AddrRange THEN
                        next_state <= PROG_PREL;
                    ELSIF Instruct'EVENT AND Instruct = ispex THEN
                        next_state <= IDLE;
                    ELSE
                        next_state <= ISP_MODE;
                    END IF;
                WHEN PROG_PREL   =>
                    IF Instruct'EVENT AND Instruct = fpgm AND ISP THEN
                        next_state <= PROG;
                    ELSIF Instruct'EVENT AND Instruct = ispex THEN
                        next_state <= IDLE;
                    END IF;

                WHEN PROG      =>
                   IF rising_edge(PDONE) THEN
                       next_state <= ISP_MODE;
                   END IF;

                WHEN ERASE      =>
                   IF rising_edge(EDONE) THEN
                       next_state <= ISP_MODE;
                   END IF;
            END CASE;
        END PROCESS StateGen_ISP;

        read_dc: PROCESS (Clock, CENeg, RESETIn)
        BEGIN
            IF rising_edge(Clock) AND CENeg = '0' AND RESETIn = '1' THEN
                read_out <= '1', '0' AFTER 1 ns;
            END IF;

        END PROCESS read_dc;

    ---------------------------------------------------------------------------
    --FSM Output generation and general funcionality
    ---------------------------------------------------------------------------
        Functional: PROCESS(TCK, TDI, Instruct, EDONE, PDONE, read_out,
                                Clock, RESETIn, change_addr, BSReg)

            VARIABLE oe          : boolean := FALSE;
            VARIABLE data_cnt    : NATURAL := 0;
            VARIABLE addr_cnt    : NATURAL := 0;
            VARIABLE data_out    : std_logic_vector(7 downto 0);
            VARIABLE write_addr  : NATURAL RANGE 0 TO AddrRANGE;

            VARIABLE AddrLo      : NATURAL RANGE 0 to MemSize;
            VARIABLE AddrHi      : NATURAL RANGE 0 to MemSize;

        BEGIN
            oe := rising_edge(read_out);

            IF rising_edge(change_addr) THEN
                write_addr := Address;
            END IF;

            IF RESETIn = '0' THEN
                Data_zd <= (OTHERS => 'Z');
                data_cnt := 0;
                addr_cnt := 0;
                CEONeg_zd <= '1';
            END IF;

            CASE current_state IS
                WHEN IDLE   =>
                    ProgStart <= FALSE;

                    IF oe THEN
                        IF ReadProt THEN
                            Data_zd <= (OTHERS => 'Z');
                            data_cnt := 0;
                            addr_cnt := 0;
                            CEONeg_zd <= '1';
                        ELSE
                            IF addr_cnt <= MemSize THEN
                                IF Mem(addr_cnt) > -1 THEN
                                    data_out := to_slv(Mem(addr_cnt),8);
                                ELSE
                                    data_out := "XXXXXXXX";
                                END IF;
                                IF Parallel THEN
                                    Data_zd   <= data_out;
                                    addr_cnt  := addr_cnt + 1;
                                    CEONeg_zd <= '1';
                                ELSE
                                    Data_zd(0)  <= data_out(data_cnt);
                                    Data_zd(7 downto 1) <= (OTHERS => 'Z');
                                    data_cnt := data_cnt + 1;
                                    IF data_cnt = 8 THEN
                                        data_cnt := 0;
                                        addr_cnt := addr_cnt + 1;
                                        CEONeg_zd <= '1';
                                    END IF;
                                END IF;
                            ELSE
                                addr_cnt := addr_cnt;
                                CEONeg_zd <= '0';
                            END IF;
                        END IF;
                    END IF;

                WHEN ISP_MODE   =>
                    IF Instruct'EVENT AND Instruct = ferase AND ISP THEN
                        ESTART  <= '0', '1' AFTER 1 ns;
                        Mem := (OTHERS => -1);
                    ELSIF Instruct'EVENT AND Instruct = fpgm AND ISP THEN
                            PSTART  <= '0', '1' AFTER 1 ns;
                            ADDRHILO_ROW(write_addr, AddrLo, AddrHi);
                            Mem(AddrLo TO AddrHi) := (OTHERS => -1);
                    ELSIF Instruct'EVENT AND Instruct = fdata3
                    AND ISP AND Address = AddrRange THEN
                        Configure <= TRUE;
                    END IF;

                WHEN ERASE      =>
                    IF rising_edge(EDONE) THEN
                        Mem      := (OTHERS => MaxData);
                        ChipErased <= TRUE;
                        ProgStart <= FALSE;
                    END IF;

                WHEN PROG_PREL  =>
                    IF Instruct'EVENT AND Instruct = fpgm AND ISP THEN
                        PSTART  <= '0', '1' AFTER 1 ns;
                    ELSIF Instruct'EVENT AND Instruct = ispex THEN
                        Configure <= FALSE;
                    END IF;

                WHEN PROG       =>
                    IF rising_edge (PDONE) THEN
                        IF Configure THEN
                            CASE ConfReg IS
                                WHEN "111"  =>
                                    Parallel <= false;
                                    ReadProt <= false;
                                WHEN "101"  =>
                                    Parallel <= true;
                                    ReadProt <= false;
                                WHEN "011"  =>
                                    ReadProt <= true;
                                WHEN others =>
                                    NULL;
                            END CASE;
                            Configure <= FALSE;
                        ELSIF ChipErased OR ProgStart THEN
                            ADDRHILO_ROW(write_addr, AddrLo, AddrHi);
                            FOR I IN AddrLo TO AddrHi LOOP
                                Mem(I) := WByte(I-AddrLo);
                            END LOOP;
                            ChipErased <= FALSE;
                            ProgStart  <= TRUE;
                        END IF;
                    END IF;
            END CASE;

        IF Instruct = extest OR Instruct = clamp THEN
                Data_zd(4) <=  BSReg(24);
                CFNeg_zd   <=  BSReg(22);
                Data_zd(6) <=  BSReg(17);
                Data_zd(7) <=  BSReg(14);
                CEONeg_zd  <=  BSReg(12);
                Data_zd(5) <=  BSReg(10);
                Data_zd(3) <=  BSReg(8 );
                Data_zd(1) <=  BSReg(6 );
                Data_zd(0) <=  BSReg(4 );
                Data_zd(2) <=  BSReg(2 );
        END IF;

        IF Instruct = highz THEN
            Data_zd   <= (others => 'Z');
            CFNeg_zd  <= 'Z';
        END IF;

        END PROCESS Functional;

        ------------------------------------------------------------------------
        -- Path Delay Section for Data Port signal
        ------------------------------------------------------------------------
        RESETNeg_PathDelay_Gen : PROCESS(RESETNeg_zd)

                VARIABLE RESETNeg_GlitchData     : VitalGlitchDataType;

            BEGIN
                VitalPathDelay01(
                    OutSignal           => RESETOut,
                    OutSignalName       => "RESETNeg",
                    OutTemp             => RESETNeg_zd,
                    GlitchData          => RESETNeg_GlitchData,
                    Mode                => VitalTransport,
                    Paths               => (
                    0 => (InputChangeTime => TCK'LAST_EVENT,
                        PathDelay       => tpd_TCK_RESETNeg,
                        PathCondition   => TRUE)
                    )
                );
            END PROCESS;

        ------------------------------------------------------------------------
        -- Path Delay Section for Data Port signal
        ------------------------------------------------------------------------
        DATA_PathDelay_Gen : FOR i IN Data_zd'RANGE GENERATE

            PROCESS(Data_zd(i))

                VARIABLE D_GlitchData     : VitalGlitchDataType;

            BEGIN
                VitalPathDelay01Z(
                    OutSignal           => Data(i),
                    OutSignalName       => "DATA",
                    OutTemp             => Data_zd(i),
                    GlitchData          => D_GlitchData,
                    Mode                => VitalTransport,
                    Paths               => (
                    0 => (InputChangeTime => Clock'LAST_EVENT,
                        PathDelay       => VitalExtendToFillDelay(tpd_CLK_D0),
                        PathCondition   => RESETIn = '1' AND CENeg = '0'),
                    1 => (InputChangeTime => RESETIn'LAST_EVENT,
                        PathDelay       => tpd_RESETNeg_D0,
                        PathCondition   => CENeg ='0' ),
                    2 => (InputChangeTime => CENeg'LAST_EVENT,
                        PathDelay       => tpd_CENeg_D0,
                        PathCondition   => true)
                    )
                );
            END PROCESS;
        END GENERATE DATA_PathDelay_Gen;

        ------------------------------------------------------------------------
        -- Path Delay Section for CEONeg Port signal
        ------------------------------------------------------------------------
        CEONeg_OUT: PROCESS(CEONeg_zd)

            -- Output Glitch Detection Variables
            VARIABLE CEONeg_GlitchData   : VitalGlitchDataType;

        BEGIN

            VitalPathDelay01Z (
                OutSignal       => CEONeg,
                OutSignalName   => "CEONeg",
                OutTemp         => CEONeg_zd,
                GlitchData      => CEONeg_GlitchData,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Paths           => (
                    0 => (InputChangeTime   => Clock'LAST_EVENT,
                        PathDelay         =>
                                        VitalExtendToFillDelay(tpd_CLK_CEONeg),
                        PathCondition     => RESETIn = '1' AND CENeg = '0'),
                    1 => (InputChangeTime => RESETIn'LAST_EVENT,
                        PathDelay       => tpd_RESETNeg_CEONeg,
                        PathCondition   => CENeg ='0' ),
                    2 => (InputChangeTime => CENeg'LAST_EVENT,
                        PathDelay       => tpd_CENeg_CEONeg,
                        PathCondition   => true)
                )
            );
        END PROCESS CEONeg_OUT;

        ------------------------------------------------------------------------
        -- Path Delay Section for CFNeg Port signal
        ------------------------------------------------------------------------
        CFNeg_OUT: PROCESS(CFNeg_zd)

            -- Output Glitch Detection Variables
            VARIABLE CFNeg_GlitchData   : VitalGlitchDataType;

        BEGIN

            VitalPathDelay01Z (
                OutSignal       => CFNeg,
                OutSignalName   => "CFNeg",
                OutTemp         => CFNeg_zd,
                GlitchData      => CFNeg_GlitchData,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Paths           => (
                    0 => (InputChangeTime   => TCK'LAST_EVENT,
                          PathDelay         => tpd_TCK_CFNeg,
                          PathCondition     => TRUE)
                )
            );
        END PROCESS CFNeg_OUT;

        ------------------------------------------------------------------------
        -- JTAG Path Delay Section
        ------------------------------------------------------------------------
        TDO_OUT: PROCESS(TDO_zd)

            -- Output Glitch Detection Variables
            VARIABLE TDO_GlitchData   : VitalGlitchDataType;

        BEGIN

            VitalPathDelay01Z (
                OutSignal       => TDO,
                OutSignalName   => "TDO",
                OutTemp         => TDO_zd,
                GlitchData      => TDO_GlitchData,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Paths           => (
                    0 => (InputChangeTime   => TCK'LAST_EVENT,
                          PathDelay         => tpd_TCK_TDO,
                          PathCondition     => TRUE)
                )
            );
        END PROCESS TDO_OUT;

    END BLOCK Behavior;

END vhdl_behavioral;