xc18v04.vhd

vhdl cod for ram.For sp3e

    BEGIN

    ---------------------------------------------------------------------------
    --Power Up time
    ---------------------------------------------------------------------------
        PoweredUp <= '1' AFTER tdevice_VCC;

    ---------------------------------------------------------------------------
    --Power On time
    ---------------------------------------------------------------------------
        PowerOnReset: PROCESS (PoweredUp)
        BEGIN
            IF PoweredUp = '1' THEN
                PoweredOn <= '1' AFTER tdevice_OER;
            ELSE
                PoweredOn <= '0';
            END IF;
        END PROCESS PowerOnReset;

    ---------------------------------------------------------------------------
    -- VITAL Timing Checks Procedures
    ---------------------------------------------------------------------------
        VITALTimingCheck:  PROCESS(Clock, RESETIn, CENeg, TCK, TMS, TDI)

         -- Timing Check Variables
            VARIABLE TD_CENeg_CLK     : VitalTimingDataType;
            VARIABLE Tviol_CENeg_CLK  : X01 := '0';

            VARIABLE TD_RESETNeg_CENeg    : VitalTimingDataType;
            VARIABLE Tviol_RESETNeg_CENeg : X01 := '0';

            VARIABLE TD_TMS_TCK       : VitalTimingDataType;
            VARIABLE Tviol_TMS_TCK    : X01 := '0';

            VARIABLE TD_TDI_TCK       : VitalTimingDataType;
            VARIABLE Tviol_TDI_TCK    : X01 := '0';

            VARIABLE PD_CLK           : VitalPeriodDataType
                                                        := VitalPeriodDataInit;
            VARIABLE Pviol_CLK        : X01 := '0';

            VARIABLE PD_CENeg         : VitalPeriodDataType
                                                        := VitalPeriodDataInit;
            VARIABLE Pviol_CENeg      : X01 := '0';

            VARIABLE PD_RESETNeg      : VitalPeriodDataType
                                                        := VitalPeriodDataInit;
            VARIABLE Pviol_RESETNeg   : X01 := '0';

            VARIABLE PD_TCK           : VitalPeriodDataType
                                                        := VitalPeriodDataInit;
            VARIABLE Pviol_TCK        : X01 := '0';

            VARIABLE PD_TCK_BYPSS     : VitalPeriodDataType
                                                        := VitalPeriodDataInit;
            VARIABLE Pviol_TCK_BYPSS  : X01 := '0';

            VARIABLE Violation        : X01 := '0';

        BEGIN
    ---------------------------------------------------------------------------
    -- Timing Check Section
    ---------------------------------------------------------------------------
        IF TimingChecksOn THEN

                VitalSetupHoldCheck (
                    TestSignal      => CENeg,
                    TestSignalName  => "CENeg",
                    RefSignal       => Clock,
                    RefSignalName   => "Clock",
                    SetupHigh       => tsetup_CENeg_CLK,
                    SetupLow        => tsetup_CENeg_CLK,
                    CheckEnabled    => true,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_CENeg_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_CENeg_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => TMS,
                    TestSignalName  => "TMS",
                    RefSignal       => TCK,
                    RefSignalName   => "TCK",
                    SetupHigh       => tsetup_TMS_TCK,
                    SetupLow        => tsetup_TMS_TCK,
                    HoldHigh        => thold_TMS_TCK,
                    HoldLow         => thold_TMS_TCK,
                    CheckEnabled    => true,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_TMS_TCK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_TMS_TCK );

                VitalSetupHoldCheck (
                    TestSignal      => TDI,
                    TestSignalName  => "TDI",
                    RefSignal       => TCK,
                    RefSignalName   => "TCK",
                    SetupHigh       => tsetup_TDI_TCK,
                    SetupLow        => tsetup_TDI_TCK,
                    HoldHigh        => thold_TDI_TCK,
                    HoldLow         => thold_TDI_TCK,
                    CheckEnabled    => true,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_TDI_TCK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_TDI_TCK );

                VitalPeriodPulseCheck (
                    TestSignal      =>  Clock,
                    TestSignalName  =>  "Clock",
                    Period          =>  tperiod_CLK,
                    PulseWidthLow   =>  tpw_CLK_negedge,
                    PulseWidthHigh  =>  tpw_CLK_posedge,
                    PeriodData      =>  PD_CLK,
                    XOn             =>  XOn,
                    MsgOn           =>  MsgOn,
                    Violation       =>  Pviol_CLK,
                    HeaderMsg       =>  InstancePath & PartID,
                    CheckEnabled    =>  CENeg='0' AND RESETIn = '1');

                VitalPeriodPulseCheck (
                    TestSignal      =>  CENeg,
                    TestSignalName  =>  "CENeg",
                    PulseWidthHigh  =>  tpw_CENeg_posedge,
                    PeriodData      =>  PD_CENeg,
                    XOn             =>  XOn,
                    MsgOn           =>  MsgOn,
                    Violation       =>  Pviol_CENeg,
                    HeaderMsg       =>  InstancePath & PartID,
                    CheckEnabled    =>  true);

                VitalPeriodPulseCheck (
                    TestSignal      =>  RESETIn,
                    TestSignalName  =>  "OE/RESETNeg",
                    PulseWidthHigh  =>  tpw_RESETNeg_negedge,
                    PeriodData      =>  PD_RESETNeg,
                    XOn             =>  XOn,
                    MsgOn           =>  MsgOn,
                    Violation       =>  Pviol_RESETNeg,
                    HeaderMsg       =>  InstancePath & PartID,
                    CheckEnabled    =>  true);

                VitalPeriodPulseCheck (
                    TestSignal      =>  TCK,
                    TestSignalName  =>  "JTAG Clock",
                    Period          =>  tperiod_TCK_BYPSS_EQ_0,
                    PeriodData      =>  PD_TCK,
                    XOn             =>  XOn,
                    MsgOn           =>  MsgOn,
                    Violation       =>  Pviol_TCK,
                    HeaderMsg       =>  InstancePath & PartID,
                    CheckEnabled    =>  BYPSS = '0' );

                VitalPeriodPulseCheck (
                    TestSignal      =>  TCK,
                    TestSignalName  =>  "JTAG Clock",
                    Period          =>  tperiod_TCK_BYPSS_EQ_1,
                    PeriodData      =>  PD_TCK_BYPSS,
                    XOn             =>  XOn,
                    MsgOn           =>  MsgOn,
                    Violation       =>  Pviol_TCK_BYPSS,
                    HeaderMsg       =>  InstancePath & PartID,
                    CheckEnabled    =>  BYPSS = '1' );

                Violation := Tviol_CENeg_CLK        OR
                              Tviol_RESETNeg_CENeg  OR
                              Tviol_TMS_TCK         OR
                              Tviol_TDI_TCK         OR
                              Pviol_CLK             OR
                              Pviol_CENeg           OR
                              Pviol_RESETNeg        OR
                              Pviol_TCK             OR
                              Pviol_TCK_BYPSS;

                Viol  <=  Violation;

                ASSERT Violation = '0'
                    REPORT InstancePath & partID & ": simulation may be" &
                    " inaccurate due to timing violations"
                    SEVERITY WARNING;
        END IF;
        END PROCESS VITALTimingCheck;

    ---------------------------------------------------------------------------
    -- JTAG
    ---------------------------------------------------------------------------
        JTAG : PROCESS (TDI, TMS, TCK, PoweredOn)

            TYPE tap_state_type IS (Test_Logic_Reset,
                                    Run_Test_Idle,
                                    Select_DR_Scan,
                                    Capture_DR,
                                    Shift_DR,
                                    Exit1_DR,
                                    Pause_DR,
                                    Exit2_DR,
                                    Update_DR,
                                    Select_IR_Scan,
                                    Capture_IR,
                                    Shift_IR,
                                    Exit1_IR,
                                    Pause_IR,
                                    Exit2_IR,
                                    Update_IR
                                    );

            VARIABLE TAP_state   : tap_state_type;

            VARIABLE BYReg       : std_logic := '0';
            VARIABLE BYTmp       : std_logic;
            VARIABLE IReg        : std_logic_vector(7 downto 0);
            VARIABLE ITmp        : std_logic_vector(7 downto 0);
            VARIABLE Data0Reg    : std_logic_vector(4095 downto 0)
                                                            := (OTHERS => '1');
            VARIABLE Data0Tmp    : std_logic_vector(4095 downto 0);
            VARIABLE IDReg       : std_logic_vector(31 downto 0);
            VARIABLE IDTmp       : std_logic_vector(31 downto 0);
            VARIABLE AddrReg     : NATURAL RANGE 0 TO AddrRange := 0;
            VARIABLE AddrTmp     : std_logic_vector(15 downto 0);
            VARIABLE ConfTmp     : std_logic_vector(2 downto 0);
            VARIABLE USEReg1     : std_logic_vector(15 downto 0)
                                                            := (OTHERS => '1');
            VARIABLE USEReg2     : std_logic_vector(15 downto 0)
                                                            := (OTHERS => '1');
            VARIABLE USETmp      : std_logic_vector(31 downto 0);
            VARIABLE BSTmp       : std_logic_vector(24 downto 0)
                                        := (others => '1');

            VARIABLE Byte_slv    : std_logic_vector(7 downto 0);

            VARIABLE TDOTmp      : std_logic;

            VARIABLE Shift       : BOOLEAN := false;
            VARIABLE UpdateIR    : BOOLEAN := false;
            VARIABLE UpdateDR    : BOOLEAN := false;

        BEGIN
    ----------------------------------------------------------------------------
    -- Functional Section
    ----------------------------------------------------------------------------
            -- Power Up & Reset JTAG
            IF rising_edge(PoweredOn) THEN
                TAP_state := Test_Logic_Reset;
                Shift := false;
                UpdateIR := false;
                UpdateDR := false;
                Instruct <= idcode;
                IReg  := "11111110";
                IDReg  := to_slv(DeviceID,32);
                USEReg1 := to_slv(UserID1,16);
                USEReg2 := to_slv(UserID2,16);
            END IF;

            -- TAP State Machine
            IF rising_edge(TCK) THEN
                CASE TAP_state IS
                    WHEN Test_Logic_Reset =>
                        IF TMS = '1' THEN
                            TAP_state := Test_Logic_Reset;
                            IReg      := "11111110";
                            IDReg     := to_slv(DeviceID,32);
                            Instruct  <= idcode;
                        ELSE
                            TAP_state := Run_Test_Idle;
                        END IF;
                    WHEN Run_Test_Idle =>
                        IF TMS = '1' THEN
                            TAP_state := Select_DR_Scan;
                        ELSE
                            TAP_state := Run_Test_Idle;
                        END IF;
                    WHEN Select_DR_Scan =>
                        IF TMS = '1' THEN
                            TAP_state := Select_IR_Scan;
                        ELSE
                            TAP_state := Capture_DR;
                            CASE Instruct IS
                                WHEN bypass     =>
                                    BYTmp := BYReg;
                                WHEN sample_preload =>
                                    BSTmp := BSReg;
                                    BSTmp(20) := RESETIn;
                                    BSTmp(15) := CENeg;
                                    BSTmp(0 ) := Clock;

                                    BSReg <= BSTmp;
                                WHEN extest     =>
                                    BSTmp := BSReg;
                                    BSTmp(20) := RESETIn;
                                    BSTmp(15) := CENeg;
                                    BSTmp(0 ) := Clock;

                                    BSReg <= BSTmp;
                                WHEN clamp      =>
                                    BYTmp    := BYReg;
                                WHEN highz      =>
                                    BYTmp    := BYReg;
                                WHEN idcode     =>
                                    IDTmp    := IDReg;
                                WHEN usercode   =>
                                    USETmp(15 downto 0)  := USEReg1;
                                    USETmp(31 downto 16) := USEReg2;
                                WHEN faddr      =>
                                    AddrTmp  := to_slv(AddrReg, 16);
                                WHEN fdata0     =>
                                    Data0Tmp := Data0Reg;
                                WHEN fdata3     =>
                                    ConfTmp  := ConfReg;
                                WHEN others     =>
                                    NULL;
                            END CASE;
                        END IF;
                    WHEN Capture_DR =>
                        IF TMS = '1' THEN
                            TAP_state := Exit1_DR;
                            Shift := false;
                        ELSE
                            TAP_state := Shift_DR;
                            CASE Instruct IS
                                WHEN bypass =>
                                    TDOTmp := BYTmp;
                                    BYTmp  := TDI;
                                    Shift  := true;
                                WHEN sample_preload =>
                                    TDOTmp := BSTmp(24);
                                    FOR I IN 24 DOWNTO 1 LOOP
                                        BSTmp(i) := BSTmp(i-1);
                                    END LOOP;
                                    BSTmp(0) := TDI;
                                    Shift := true;
                                WHEN extest =>
                                    TDOTmp := BSTmp(24);
                                    FOR I IN 24 DOWNTO 1 LOOP
                                        BSTmp(i) := BSTmp(i-1);
                                    END LOOP;
                                    BSTmp(0) := TDI;
                                    Shift := true;
                                WHEN clamp =>
                                    TDOTmp := BYTmp;
                                    BYTmp := TDI;
                                    Shift := true;
                                WHEN highz =>
                                    TDOTmp := BYTmp;