xc18v04.vhd

vhdl cod for ram.For sp3e

-------------------------------------------------------------------------------
--  File Name: xc18v04.vhd
-------------------------------------------------------------------------------
--  Copyright (C) 2007 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY:
--
--  version: |  author:        | mod date: |  changes made:
--    V1.0     D.Stanojkovic     07 Oct 10    Inital Release
--
-------------------------------------------------------------------------------
--  PART DESCRIPTION:
--
--  Library:    RAM
--  Technology: CMOS
--  Part:       XC18V04
--
--  Description: 4 Mbits In-System Programmable Configuration 3.3V PROM
-------------------------------------------------------------------------------
--  Known Bugs:
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
    USE IEEE.std_logic_1164.ALL;
    USE IEEE.VITAL_timing.ALL;
    USE IEEE.VITAL_primitives.ALL;
    USE STD.textio.ALL;

LIBRARY FMF;
    USE FMF.gen_utils.all;
    USE FMF.conversions.all;
-------------------------------------------------------------------------------
-- ENTITY DECLARATION
-------------------------------------------------------------------------------
ENTITY xc18v04 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_CLK            : VitalDelayType01  := VitalZeroDelay01;
        tipd_RESETNeg       : VitalDelayType01  := VitalZeroDelay01;
        tipd_CENeg          : VitalDelayType01  := VitalZeroDelay01;

        tipd_TMS            : VitalDelayType01  := VitalZeroDelay01;
        tipd_TCK            : VitalDelayType01  := VitalZeroDelay01;
        tipd_TDI            : VitalDelayType01  := VitalZeroDelay01;

        -- tpd delays
        tpd_RESETNeg_D0     : VitalDelayType01Z := UnitDelay01Z; -- tOE, tDF
        tpd_CENeg_D0        : VitalDelayType01Z := UnitDelay01Z; -- tCE, tDF
        tpd_CLK_D0          : VitalDelayType01  := UnitDelay01;  -- tCAC

        tpd_RESETNeg_CEONeg : VitalDelayType01Z := UnitDelay01Z;
        tpd_CENeg_CEONeg    : VitalDelayType01Z := UnitDelay01Z;
        tpd_CLK_CEONeg      : VitalDelayType01  := UnitDelay01;

        tpd_TCK_RESETNeg    : VitalDelayType01  := UnitDelay01;
        tpd_TCK_CFNeg       : VitalDelayType01Z := UnitDelay01Z;

        tpd_TCK_TDO         : VitalDelayType01Z := UnitDelay01Z; -- tDOV

        -- tsetup values: setup times
        tsetup_CENeg_CLK    : VitalDelayType    := UnitDelay; -- tSCE

        tsetup_TMS_TCK      : VitalDelayType    := UnitDelay; -- tMSS
        tsetup_TDI_TCK      : VitalDelayType    := UnitDelay; -- tDIS

        -- thold values: hold times
        thold_TMS_TCK       : VitalDelayType    := UnitDelay; -- tMSH
        thold_TDI_TCK       : VitalDelayType    := UnitDelay; -- tDIH

        -- tpw values: pulse widths
        tpw_CLK_posedge     : VitalDelayType    := UnitDelay; -- tHC
        tpw_CLK_negedge     : VitalDelayType    := UnitDelay; -- tLC
        tpw_CENeg_posedge   : VitalDelayType    := UnitDelay; -- tHCE
        tpw_RESETNeg_negedge: VitalDelayType    := UnitDelay; -- tHOE

        -- tperiod min
        tperiod_CLK         : VitalDelayType    := UnitDelay; -- tCYC

        tperiod_TCK_BYPSS_EQ_0  : VitalDelayType    := UnitDelay; -- tCKMIN1
        tperiod_TCK_BYPSS_EQ_1  : VitalDelayType    := UnitDelay; -- tCKMIN2

        --tdevice values: values for internal delays
            -- Power-up
        tdevice_VCC          : VitalDelayType    := 50 ms;  --tVCC

            -- Power-on Reset
        tdevice_OER          : VitalDelayType    := 1 ms;   --tOER

            -- In-System Programming
        tdevice_ISP          : VitalDelayType    := 14 ms;  --tISP

            -- Erase all sectors
        tdevice_ERS          : VitalDelayType    := 15000 ms; --tERS

        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;

        -- memory file to be loaded
        LongTiming          : BOOLEAN   := TRUE;

        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        -- inputs
        CLK             : IN    std_ulogic := 'U';
        RESETNeg        : INOUT std_ulogic := 'U';
        CENeg           : IN    std_ulogic := 'U';
        TCK             : IN    std_ulogic := 'U';
        TMS             : IN    std_ulogic := 'U';
        TDI             : IN    std_ulogic := 'U';

        -- outputs
        D0              : OUT   std_ulogic := 'U';
        D1              : OUT   std_ulogic := 'U';
        D2              : OUT   std_ulogic := 'U';
        D3              : OUT   std_ulogic := 'U';
        D4              : OUT   std_ulogic := 'U';
        D5              : OUT   std_ulogic := 'U';
        D6              : OUT   std_ulogic := 'U';
        D7              : OUT   std_ulogic := 'U';
        CFNeg           : OUT   std_ulogic := 'U';
        CEONeg          : OUT   std_ulogic := 'U';
        TDO             : OUT   std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of xc18v04 : ENTITY IS TRUE;
END xc18v04;
-------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
-------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of xc18v04 IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT partID         : STRING  := "xc18v04";
    CONSTANT HiAddrBit      : NATURAL := 18;
    CONSTANT MaxData        : NATURAL := 16#FF#;
    CONSTANT DataSize       : NATURAL := 7;
    CONSTANT DeviceID       : NATURAL := 16#05026093#;
    CONSTANT UserID1        : NATURAL := 16#FFFF#;
    CONSTANT UserID2        : NATURAL := 16#FFFF#;

    CONSTANT PageSize       : NATURAL := 15;
    CONSTANT PageNum        : NATURAL := 31;
    CONSTANT RowSize        : NATURAL := (PageNum+1)*(PageSize+1)-1;
    CONSTANT RowNum         : NATURAL := 1023;
    CONSTANT AddrRange      : NATURAL := (RowNum+1)*(PageNum+1);  --8000
    CONSTANT MemSize        : NATURAL := (RowNum+1)*(RowSize+1)-1;

    -- interconnect path delay signals
    SIGNAL CLK_ipd         : std_ulogic := 'U';
    SIGNAL RESETNeg_ipd    : std_ulogic := 'U';
    SIGNAL CENeg_ipd       : std_ulogic := 'U';
    SIGNAL TCK_ipd         : std_ulogic := 'U';
    SIGNAL TMS_ipd         : std_ulogic := 'U';
    SIGNAL TDI_ipd         : std_ulogic := 'U';

    -- nwv
    SIGNAL CLK_nwv         : std_ulogic := 'U';
    SIGNAL RESETNeg_nwv    : std_logic  := 'U';
    SIGNAL CENeg_nwv       : std_ulogic := 'U';
    SIGNAL TCK_nwv         : std_ulogic := 'U';
    SIGNAL TMS_nwv         : std_ulogic := 'U';
    SIGNAL TDI_nwv         : std_ulogic := 'U';

    -- internal delays
    SIGNAL tVCC_in         : std_ulogic := '0';
    SIGNAL tVCC_out        : std_ulogic := '0';
    SIGNAL tOER_in         : std_ulogic := '0';
    SIGNAL tOER_out        : std_ulogic := '0';
    SIGNAL tISP_in         : std_ulogic := '0';
    SIGNAL tISP_out        : std_ulogic := '0';
    SIGNAL tERS_in         : std_ulogic := '0';
    SIGNAL tERS_out        : std_ulogic := '0';

BEGIN
    ---------------------------------------------------------------------------
    -- Internal Delays
    ---------------------------------------------------------------------------
    -- Artificial VITAL primitives to incorporate internal delays
    VCC    :VitalBuf(tVCC_out,  tVCC_in,    (tdevice_VCC     ,UnitDelay));
    OER    :VitalBuf(tOER_out,  tOER_in,    (tdevice_OER     ,UnitDelay));
    ISP    :VitalBuf(tISP_out,  tISP_in,    (tdevice_ISP     ,UnitDelay));
    ERS    :VitalBuf(tERS_out,  tERS_in,    (tdevice_ERS     ,UnitDelay));

    ---------------------------------------------------------------------------
    -- Wire Delays
    ---------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (CLK_ipd,      CLK,        tipd_CLK);
        w_2 : VitalWireDelay (RESETNeg_ipd, RESETNeg,   tipd_RESETNeg);
        w_3 : VitalWireDelay (CENeg_ipd,    CENeg,      tipd_CENeg);
        w_4 : VitalWireDelay (TCK_ipd,      TCK,        tipd_TCK);
        w_5 : VitalWireDelay (TMS_ipd,      TMS,        tipd_TMS);
        w_6 : VitalWireDelay (TDI_ipd,      TDI,        tipd_TDI);

    END BLOCK;

    CLK_nwv        <= To_UX01(CLK_ipd       );
    RESETNeg_nwv   <= To_UX01(RESETNeg_ipd  );
    CENeg_nwv      <= To_UX01(CENeg_ipd     );
    TCK_nwv        <= To_UX01(TCK_ipd       );
    TMS_nwv        <= To_UX01(TMS_ipd       );
    TDI_nwv        <= To_UX01(TDI_ipd       );

    ---------------------------------------------------------------------------
    -- Main Behavior Block
    ---------------------------------------------------------------------------
    Behavior: BLOCK
        PORT (
            Clock           : IN    std_logic;
            RESETIn         : IN    std_logic;
            RESETOut        : OUT   std_logic;
            CENeg           : IN    std_logic;
            TCK             : IN    std_logic;
            TMS             : IN    std_logic;
            TDI             : IN    std_logic;

            Data            : OUT   std_logic_vector(7 downto 0);
            CFNeg           : OUT   std_logic;
            CEONeg          : OUT   std_logic;
            TDO             : OUT   std_logic
        );

        PORT MAP (
            Clock   => CLK_nwv  ,
            RESETIn => RESETNeg_nwv   ,
            CENeg   => CENeg_nwv,
            TCK     => TCK_nwv  ,
            TMS     => TMS_nwv  ,
            TDI     => TDI_nwv  ,

            RESETOut=> RESETNeg,
            Data(0) => D0      ,
            Data(1) => D1      ,
            Data(2) => D2      ,
            Data(3) => D3      ,
            Data(4) => D4      ,
            Data(5) => D5      ,
            Data(6) => D6      ,
            Data(7) => D7      ,
            CFNeg   => CFNeg   ,
            CEONeg  => CEONeg  ,
            TDO     => TDO
        );

        -- State Machine : State_Type
        TYPE state_type IS (
                            IDLE,
                            ISP_MODE,
                            ERASE,
                            PROG_PREL,
                            PROG
                           );

        -- JTAG Instructions
        TYPE Instruction IS (
                             bypass,
                             sample_preload,
                             extest,
                             clamp,
                             highz,
                             idcode,
                             usercode,
                             config,
                             ispen,
                             ferase,
                             fpgm,
                             ispex,
                             faddr,
                             fdata0,
                             fdata3
                            );

        --zero delay signals
        SIGNAL Data_zd     : std_logic_vector(7 DOWNTO 0) := (OTHERS => 'Z');
        SIGNAL CEONeg_zd   : std_logic := 'Z';
        SIGNAL RESETNeg_zd : std_logic := 'Z';
        SIGNAL CFNeg_zd    : std_logic := 'Z';
        SIGNAL TDO_zd      : std_logic := 'Z';

        -- timing check violation
        SIGNAL Viol : X01 := '0';

        TYPE WByteType IS ARRAY (0 TO RowSize) OF INTEGER RANGE -1 TO MaxData;
        --memory definition
        TYPE MemArray  IS ARRAY (0 TO MemSize) OF INTEGER RANGE -1 TO MaxData;

        SHARED VARIABLE Mem       : MemArray  := (OTHERS => MaxData);
        SHARED VARIABLE ConfMode  : std_logic_vector(2 downto 0)
                                                            := (OTHERS => '1');

        SIGNAL WByte            : WByteType := (OTHERS => 0);

        SIGNAL Instruct  : Instruction := idcode;
        SIGNAL BSReg     : std_logic_vector(24 downto 0)
                                                := "1101101110111011111111110";
        SIGNAL ConfReg   : std_logic_vector(2 downto 0) := (OTHERS => '1');

        -- states
        SIGNAL current_state    : state_type := IDLE;
        SIGNAL next_state       : state_type := IDLE;

        --Command Register
        SIGNAL read_out         : std_logic := '0';

        -- ISP enable signal
        SIGNAL ISP              : boolean   := FALSE;

        -- BYPASS enable signal
        SIGNAL BYPSS            : std_logic := '0';

        SIGNAL change_addr      : std_logic := '0';

        SIGNAL Address          : NATURAL RANGE 0 TO AddrRange := 0;

        -- powerup
        SIGNAL PoweredUp : std_logic := '0';
        SIGNAL PoweredOn : std_logic := '0';

        --FSM control signals
        SIGNAL PDONE            : std_logic := '0'; --Programming Done
        SIGNAL PSTART           : std_logic := '0'; --Start Programming

        SIGNAL EDONE            : std_logic := '0'; --Erase Done
        SIGNAL ESTART           : std_logic := '0'; --Start Erase

        SIGNAL ChipErased       : BOOLEAN   := FALSE;
        SIGNAL ProgStart        : BOOLEAN   := FALSE;
        SIGNAL Parallel         : BOOLEAN   := FALSE;
        SIGNAL ReadProt         : BOOLEAN   := FALSE;
        SIGNAL Configure        : BOOLEAN   := FALSE;

        PROCEDURE ADDRHILO_ROW(
            VARIABLE   Addr     : IN  NATURAL RANGE 0 TO AddrRange-1;
            VARIABLE   AddrLOW  : OUT NATURAL RANGE 0 to MemSize;
            VARIABLE   AddrHIGH : OUT NATURAL RANGE 0 to MemSize) IS
            VARIABLE   row      : NATURAL RANGE 0 TO RowNum;
        BEGIN
            row      := Addr/(PageNum+1);
            AddrLOW  := row*(PageNum+1)*(PageSize+1);
            AddrHIGH := (row+1)*(PageNum+1)*(PageSize+1)-1;
        END ADDRHILO_ROW;