📄 cy7c1353b.vhd
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VitalSetupHoldCheck ( TestSignal => CKENIn, TestSignalName => "CLKENNeg", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_CLKENNeg_CLK, SetupLow => tsetup_CLKENNeg_CLK, HoldHigh => thold_CLKENNeg_CLK, HoldLow => thold_CLKENNeg_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CKENIn_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CKENIn_CLK ); VitalSetupHoldCheck ( TestSignal => ADVIn, TestSignalName => "ADV", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_ADV_CLK, SetupLow => tsetup_ADV_CLK, HoldHigh => thold_ADV_CLK, HoldLow => thold_ADV_CLK, CheckEnabled => (CKENIn ='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_ADVIn_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ADVIn_CLK ); VitalSetupHoldCheck ( TestSignal => CE1NegIn, TestSignalName => "CE1Neg", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_CE2_CLK, SetupLow => tsetup_CE2_CLK, HoldHigh => thold_CE2_CLK, HoldLow => thold_CE2_CLK, CheckEnabled => (CKENIn ='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CE1NegIn_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE1NegIn_CLK ); VitalSetupHoldCheck ( TestSignal => CE3NegIn, TestSignalName => "CE3Neg", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_CE2_CLK, SetupLow => tsetup_CE2_CLK, HoldHigh => thold_CE2_CLK, HoldLow => thold_CE2_CLK, CheckEnabled => (CKENIn ='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CE3NegIn_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE3NegIn_CLK ); VitalSetupHoldCheck ( TestSignal => CE2In, TestSignalName => "CE2", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_CE2_CLK, SetupLow => tsetup_CE2_CLK, HoldHigh => thold_CE2_CLK, HoldLow => thold_CE2_CLK, CheckEnabled => (CKENIn ='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CE2In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE2In_CLK ); VitalSetupHoldCheck ( TestSignal => RIn, TestSignalName => "R", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_R_CLK, SetupLow => tsetup_R_CLK, HoldHigh => thold_R_CLK, HoldLow => thold_R_CLK, CheckEnabled => (CKENIn ='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RIn_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RIn_CLK ); VitalSetupHoldCheck ( TestSignal => AddressIn, TestSignalName => "Address", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_A0_CLK, SetupLow => tsetup_A0_CLK, HoldHigh => thold_A0_CLK, HoldLow => thold_A0_CLK, CheckEnabled => (CKENIn ='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_AddressIn_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_AddressIn_CLK ); VitalSetupHoldCheck ( TestSignal => DatBIn, TestSignalName => "DatB", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_DQA0_CLK, SetupLow => tsetup_DQA0_CLK, HoldHigh => thold_DQA0_CLK, HoldLow => thold_DQA0_CLK, CheckEnabled => (CKENIn ='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DatBIn_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DatBIn_CLK ); VitalSetupHoldCheck ( TestSignal => DatAIn, TestSignalName => "DatA", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_DQA0_CLK, SetupLow => tsetup_DQA0_CLK, HoldHigh => thold_DQA0_CLK, HoldLow => thold_DQA0_CLK, CheckEnabled => (CKENIn ='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DatAIn_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DatAIn_CLK ); VitalPeriodPulseCheck ( TestSignal => CLKIn, TestSignalName => "CLK", Period => tperiod_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PeriodData => PD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLK, HeaderMsg => InstancePath & PartID, CheckEnabled => (CKENIn ='0') ); Violation := Pviol_CLK OR Tviol_DatAIn_CLK OR Tviol_DatBIn_CLK OR Tviol_AddressIn_CLK OR Tviol_RIn_CLK OR Tviol_CE2In_CLK OR Tviol_CE3NegIn_CLK OR Tviol_CE1NegIn_CLK OR Tviol_ADVIn_CLK OR Tviol_CKENIn_CLK OR Tviol_BWAN_CLK OR Tviol_BWBN_CLK; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY SeverityMode; END IF; -- Timing Check Section -------------------------------------------------------------------- -- Functional Section -------------------------------------------------------------------- IF (rising_edge(CLKIn) AND CKENIn = '0') THEN ASSERT (not(Is_X(BWBNIn))) REPORT InstancePath & partID & ": Unusable value for BWBN" SEVERITY SeverityMode; ASSERT (not(Is_X(BWANIn))) REPORT InstancePath & partID & ": Unusable value for BWAN" SEVERITY SeverityMode; ASSERT (not(Is_X(RIn))) REPORT InstancePath & partID & ": Unusable value for R" SEVERITY SeverityMode; ASSERT (not(Is_X(ADVIn))) REPORT InstancePath & partID & ": Unusable value for ADV" SEVERITY SeverityMode; ASSERT (not(Is_X(CE2In))) REPORT InstancePath & partID & ": Unusable value for CE2" SEVERITY SeverityMode; ASSERT (not(Is_X(CE1NegIn))) REPORT InstancePath & partID & ": Unusable value for CE1Neg" SEVERITY SeverityMode; ASSERT (not(Is_X(CE3NegIn))) REPORT InstancePath & partID & ": Unusable value for CE3Neg" SEVERITY SeverityMode; -- Command Decode IF ((ADVIn = '0') AND (CE1NegIn = '1' OR CE3NegIn = '1' OR CE2In = '0')) THEN command := ds; ELSIF (CE1NegIn = '0' AND CE3NegIn = '0' AND CE2In = '1' AND ADVIn = '0') THEN IF (RIn = '1') THEN command := read; ELSE command := write; END IF; ELSIF (ADVIn = '1') AND (CE1NegIn = '0' AND CE3NegIn = '0' AND CE2In = '1') THEN command := burst; ELSE ASSERT false REPORT InstancePath & partID & ": Could not decode " & "command." SEVERITY SeverityMode; END IF; wr2 := wr1; wr1 := false; -- Writing data in Memory IF (wr2) THEN IF (BWA1 = '0') THEN IF Violation = 'X' THEN MemDataA(MemAddr) := -1; ELSE MemDataA(MemAddr) := to_nat(DatAIn); END IF; END IF; IF (BWB1 = '0') THEN IF Violation = 'X' THEN MemDataB(MemAddr) := -1; ELSE MemDataB(MemAddr) := to_nat(DatBIn); END IF; END IF; END IF; -- The State Machine CASE state IS WHEN desel => CASE command IS WHEN ds => next_state <= desel; OBuf1 := (others => 'Z'); WHEN read => next_state <= begin_rd; MemAddr := to_nat(AddressIn); startaddr := MemAddr; memstart := to_nat(AddressIn(1 downto 0)); IF MemDataA(MemAddr) = -2 THEN OBuf1(8 downto 0) := (others => 'U'); ELSIF MemDataA(MemAddr) = -1 THEN OBuf1(8 downto 0) := (others => 'X'); ELSE OBuf1(8 downto 0) := to_slv(MemDataA(MemAddr),9); END IF; IF MemDataB(MemAddr) = -2 THEN OBuf1(17 downto 9) := (others => 'U');
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