cy22395.vhd

来自「Vhdl cod for a clock for sp3e」· VHDL 代码 · 共 1,293 行 · 第 1/4 页

                    PLL1A_P98    <= R_48H(1 downto 0);
                    PLL1A_P70    <= R_47H;
                    PLL1A_P0     <= R_48H(2);
                    PLL1A_En     <= R_48H(6);
                    PLL1A_DivSel <= R_48H(7);

                    PLL1B_Q      <= R_52H;
                    PLL1B_P98    <= R_54H(1 downto 0);
                    PLL1B_P70    <= R_53H;
                    PLL1B_P0     <= R_54H(2);
                    PLL1B_En     <= R_54H(6);
                    PLL1B_DivSel <= R_54H(7);
                WHEN 3 =>
                    PLL1A_Q      <= R_49H;
                    PLL1A_P98    <= R_4BH(1 downto 0);
                    PLL1A_P70    <= R_4AH;
                    PLL1A_P0     <= R_4BH(2);
                    PLL1A_En     <= R_4BH(6);
                    PLL1A_DivSel <= R_4BH(7);

                    PLL1B_Q      <= R_55H;
                    PLL1B_P98    <= R_57H(1 downto 0);
                    PLL1B_P70    <= R_56H;
                    PLL1B_P0     <= R_57H(2);
                    PLL1B_En     <= R_57H(6);
                    PLL1B_DivSel <= R_57H(7);
                WHEN OTHERS => NULL;
            END CASE;
        END PROCESS Selector01;

        Selector2: PROCESS (PLL1A_Q,PLL1A_P98,PLL1A_P70,PLL1A_P0,PLL1A_En,
                            PLL1A_DivSel,PLL1B_Q,PLL1B_P98,PLL1B_P70,PLL1B_P0,
                            PLL1B_En,PLL1B_DivSel,S2) IS
        BEGIN  -- PROCESS Selector2
            CASE S2 IS
                WHEN '0' =>
                    PLL1_Q      <= PLL1A_Q;
                    PLL1_P98    <= PLL1A_P98;
                    PLL1_P70    <= PLL1A_P70;
                    PLL1_P0     <= PLL1A_P0;
                    PLL1_En     <= PLL1A_En;
                    PLL1_DivSel <= PLL1A_DivSel;
                WHEN '1' =>
                    PLL1_Q      <= PLL1B_Q;
                    PLL1_P98    <= PLL1B_P98;
                    PLL1_P70    <= PLL1B_P70;
                    PLL1_P0     <= PLL1B_P0;
                    PLL1_En     <= PLL1B_En;
                    PLL1_DivSel <= PLL1B_DivSel;
                WHEN OTHERS => NULL;
            END CASE;
        END PROCESS Selector2;
        -----------------------------------------------------------------------
        -- PLL1 Process
        -----------------------------------------------------------------------
        PLL1 : PROCESS (XTALIN, MULT1_OUT, PLL1_OUT)
            VARIABLE clk_period   : time := 0 ns;
            VARIABLE prev_clk     : time := 0 ns;
            VARIABLE mult_period  : time := 0 ns;
            VARIABLE prev_mult    : time := 0 ns;
            VARIABLE half_per     : time := 3 ns;
        BEGIN
            -------------------------------------------------------------------
            -- Functionality Section
            -------------------------------------------------------------------
            IF rising_edge(XTALIN) THEN
                clk_period := NOW - prev_clk;
                prev_clk := NOW;
            END IF;
            IF rising_edge(MULT1_OUT) THEN
                mult_period := NOW - prev_mult;
                prev_mult := NOW;
                IF    mult_period > (clk_period + 350 ns) THEN
                    half_per := half_per - 60 ps;
                    PLL1_LOCK <= false;
                ELSIF mult_period < (clk_period - 350 ns) THEN
                    half_per := half_per + 59 ps;
                    PLL1_LOCK <= false;
                ELSIF mult_period > (clk_period + 3 ns) THEN
                    half_per := half_per - 6 ps;
                    PLL1_LOCK <= false;
                ELSIF mult_period < (clk_period - 3 ns) THEN
                    half_per := half_per + 5.9 ps;
                    PLL1_LOCK <= false;
                ELSIF mult_period > (clk_period + 300 ps) THEN
                    half_per := half_per - 600 fs;
                    PLL1_LOCK <= false;
                ELSIF mult_period < (clk_period - 300 ps) THEN
                    half_per := half_per + 590 fs;
                    PLL1_LOCK <= false;
                ELSIF mult_period > (clk_period + 30 ps) THEN
                    half_per := half_per - 60 fs;
                    PLL1_LOCK <= false;
                ELSIF mult_period < (clk_period - 30 ps) THEN
                    half_per := half_per + 59 fs;
                    PLL1_LOCK <= false;
                ELSIF mult_period > (clk_period + 3 ps) THEN
                    half_per := half_per - 6 fs;
                    PLL1_LOCK <= false;
                ELSIF mult_period < (clk_period - 3 ps) THEN
                    half_per := half_per + 5 fs;
                    PLL1_LOCK <= false;
                ELSIF NOW > 0 ns THEN
                    PLL1_LOCK <= true;
                ELSE
                    PLL1_LOCK <= false;
                END IF;
            END IF;
            IF (PLL1_En='1'AND (PdnEn = '0' OR (
                PdnEn = '1' AND SHUTDOWNNegOE_ipd = '1')))AND NOT
                PLL1_OUT'event THEN
                PLL1_OUT <= '0' AFTER half_per, '1' AFTER 2*half_per;
            END IF;
            IF (rising_edge(PLL1_OUT) OR (NOW = 0 ns))
                AND (PLL1_En = '1' AND (PdnEn = '0' OR (
                    PdnEn = '1' AND SHUTDOWNNegOE_ipd = '1'))) THEN
                PLL1_OUT <= '0' AFTER half_per, '1' AFTER 2*half_per;
            ELSIF (PLL1_En = '0') OR (
                PdnEn = '1' AND SHUTDOWNNegOE_ipd = '0') THEN
                PLL1_OUT <= 'Z';
            END IF;
        END PROCESS PLL1;

        ------------------------------------------------------------------------
        -- PLL2 Process
        ------------------------------------------------------------------------
        PLL2 : PROCESS (XTALIN, MULT2_OUT, PLL2_OUT)
            VARIABLE clk_period   : time := 0 ns;
            VARIABLE prev_clk     : time := 0 ns;
            VARIABLE mult_period  : time := 0 ns;
            VARIABLE prev_mult    : time := 0 ns;
            VARIABLE half_per     : time := 3 ns;
        BEGIN
            --------------------------------------------------------------------
            -- Functionality Section
            --------------------------------------------------------------------
            IF rising_edge(XTALIN) THEN
                clk_period := NOW - prev_clk;
                prev_clk := NOW;
            END IF;
            IF rising_edge(MULT2_OUT) THEN
                mult_period := NOW - prev_mult;
                prev_mult := NOW;
                IF    mult_period > (clk_period + 350 ns) THEN
                    half_per := half_per - 60 ps;
                    PLL2_LOCK <= false;
                ELSIF mult_period < (clk_period - 350 ns) THEN
                    half_per := half_per + 59 ps;
                    PLL2_LOCK <= false;
                ELSIF mult_period > (clk_period + 3 ns) THEN
                    half_per := half_per - 6 ps;
                    PLL2_LOCK <= false;
                ELSIF mult_period < (clk_period - 3 ns) THEN
                    half_per := half_per + 5.9 ps;
                    PLL2_LOCK <= false;
                ELSIF mult_period > (clk_period + 300 ps) THEN
                    half_per := half_per - 600 fs;
                    PLL2_LOCK <= false;
                ELSIF mult_period < (clk_period - 300 ps) THEN
                    half_per := half_per + 590 fs;
                    PLL2_LOCK <= false;
                ELSIF mult_period > (clk_period + 30 ps) THEN
                    half_per := half_per - 60 fs;
                    PLL2_LOCK <= false;
                ELSIF mult_period < (clk_period - 30 ps) THEN
                    half_per := half_per + 59 fs;
                    PLL2_LOCK <= false;
                ELSIF mult_period > (clk_period + 3 ps) THEN
                    half_per := half_per - 6 fs;
                    PLL2_LOCK <= false;
                ELSIF mult_period < (clk_period - 3 ps) THEN
                    half_per := half_per + 5 fs;
                    PLL2_LOCK <= false;
                ELSIF NOW > 0 ns THEN
                    PLL2_LOCK <= true;
                ELSE
                    PLL2_LOCK <= false;
                END IF;
            END IF;
            IF (PLL2_En = '1' AND  (PdnEn = '0' OR (
                PdnEn = '1' AND SHUTDOWNNegOE_ipd = '1')))AND NOT
                PLL2_OUT'event THEN
                PLL2_OUT <= '0' AFTER half_per, '1' AFTER 2*half_per;
            END IF;
            IF (rising_edge(PLL2_OUT) OR (NOW = 0 ns))
                AND (PLL2_En = '1' AND  (PdnEn = '0' OR (
                    PdnEn = '1' AND SHUTDOWNNegOE_ipd = '1'))) THEN
                PLL2_OUT <= '0' AFTER half_per, '1' AFTER 2*half_per;
            ELSIF (PLL2_En = '0') OR (
                PdnEn = '1' AND SHUTDOWNNegOE_ipd = '0') THEN
                PLL2_OUT <= 'Z';
            END IF;
        END PROCESS PLL2;

        -----------------------------------------------------------------------
        -- PLL3 Process
        -----------------------------------------------------------------------
        PLL3 : PROCESS (XTALIN, MULT3_OUT, PLL3_OUT)
            VARIABLE clk_period   : time := 0 ns;
            VARIABLE prev_clk     : time := 0 ns;
            VARIABLE mult_period  : time := 0 ns;
            VARIABLE prev_mult    : time := 0 ns;
            VARIABLE half_per     : time := 5 ns;
        BEGIN
            -------------------------------------------------------------------
            -- Functionality Section
            -------------------------------------------------------------------
            IF rising_edge(XTALIN) THEN
                clk_period := NOW - prev_clk;
                prev_clk := NOW;
            END IF;
            IF rising_edge(MULT3_OUT) THEN
                mult_period := NOW - prev_mult;
                prev_mult := NOW;
                IF    mult_period > (clk_period + 350 ns) THEN
                    half_per := half_per - 60 ps;
                    PLL3_LOCK <= false;
                ELSIF mult_period < (clk_period - 350 ns) THEN
                    half_per := half_per + 59 ps;
                    PLL3_LOCK <= false;
                ELSIF mult_period > (clk_period + 3 ns) THEN
                    half_per := half_per - 6 ps;
                    PLL3_LOCK <= false;
                ELSIF mult_period < (clk_period - 3 ns) THEN
                    half_per := half_per + 5.9 ps;
                    PLL3_LOCK <= false;
                ELSIF mult_period > (clk_period + 300 ps) THEN
                    half_per := half_per - 600 fs;
                    PLL3_LOCK <= false;
                ELSIF mult_period < (clk_period - 300 ps) THEN
                    half_per := half_per + 590 fs;
                    PLL3_LOCK <= false;
                ELSIF mult_period > (clk_period + 30 ps) THEN
                    half_per := half_per - 60 fs;
                    PLL3_LOCK <= false;
                ELSIF mult_period < (clk_period - 30 ps) THEN
                    half_per := half_per + 59 fs;
                    PLL3_LOCK <= false;
                ELSIF mult_period > (clk_period + 3 ps) THEN
                    half_per := half_per - 6 fs;
                    PLL3_LOCK <= false;
                ELSIF mult_period < (clk_period - 3 ps) THEN
                    half_per := half_per + 5 fs;
                    PLL3_LOCK <= false;
                ELSIF NOW > 0 ns THEN
                    PLL3_LOCK <= true;
                ELSE
                    PLL3_LOCK <= false;
                END IF;
            END IF;
            IF (PLL3_En = '1' AND (PdnEn = '0' OR (
                PdnEn = '1' AND SHUTDOWNNegOE_ipd = '1')))AND NOT
                PLL3_OUT'event THEN
                PLL3_OUT <= '0' AFTER half_per, '1' AFTER 2*half_per;
            END IF;
            IF (rising_edge(PLL3_OUT) OR (NOW = 0 ns))
                AND (PLL3_En = '1' AND (PdnEn = '0' OR (
                    PdnEn = '1' AND SHUTDOWNNegOE_ipd = '1'))) THEN
                PLL3_OUT <= '0' AFTER half_per, '1' AFTER 2*half_per;
            ELSIF (PLL3_En = '0') OR (
                PdnEn = '1' AND SHUTDOWNNegOE_ipd = '0') THEN
                PLL3_OUT <= 'Z';
            END IF;
        END PROCESS PLL3;

        -----------------------------------------------------------------------
        -- Multiplier Process
        -- The "Multiplier" actually divides the PLL_OUT signal
        -----------------------------------------------------------------------
        MULT1 : PROCESS (PLL1_OUT)
            VARIABLE    mult_in  : natural;
            VARIABLE    mult_cnt : natural;
            VARIABLE    first   : BOOLEAN := true;
        BEGIN
            mult_in := 2 * (to_nat(PLL1_P98) * 16#100# + to_nat(PLL1_P70) + 3)
                       + to_nat(PLL1_P0);
            IF PLL1_OUT /= 'Z' THEN
                IF PLL1_OUT'event THEN
                    IF first THEN
                        MULT1_OUT <= PLL1_OUT;
                        first := false;
                        mult_cnt := mult_cnt + 1;
                    ELSIF mult_cnt < mult_in THEN
                        mult_cnt := mult_cnt + 1;
                    ELSE
                        mult_cnt := 1;
                        MULT1_OUT <= NOT1(MULT1_OUT);
                    END IF;
                END IF;
            ELSE
                first := true;
                mult_cnt := 0;
                MULT1_OUT <= 'Z';
            END IF;
        END PROCESS MULT1;

        -----------------------------------------------------------------------
        -- Multiplier Process
        -- The "Multiplier" actually divides the PLL_OUT signal
        -----------------------------------------------------------------------
        MULT2 : PROCESS (PLL2_OUT)
            VARIABLE    mult_in  : natural;
            VARIABLE    mult_cnt : natural;
            VARIABLE    first   : BOOLEAN := true;
        BEGIN
            mult_in := 2 * (to_nat(PLL2_P98) * 16#100# + to_nat(PLL2_P70) + 3)
                       + to_nat(PLL2_P0);
            IF PLL2_OUT /= 'Z' THEN
                IF PLL2_OUT'event THEN
                    IF first THEN
                        MULT2_OUT <= PLL2_OUT;
                        first := false;
                        mult_cnt := mult_cnt + 1;
                    ELSIF mult_cnt < mult_in THEN
                        mult_cnt := mult_cnt + 1;
                    ELSE
                        mult_cnt := 1;
                        MULT2_OUT <= NOT1(MULT2_OUT);
                    END IF;
                END IF;
            ELSE
                first := true;
                mult_cnt := 0;
                MULT2_OUT <= 'Z';