cdc351.vhd

Vhdl cod for a clock for sp3e

--------------------------------------------------------------------------------
--  File Name: cdc351.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2000-2002 Free Model Foundry http://www.FreeModelFoundry.com/
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0     R. Munden   00 APR 03   initial release
--    V2.0     R. Munden   02 APR 13   flattened model
--    V2.1     R. Munden   08 APR 22   removed unused generic
-- 
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:    CLOCK
--  Technology: TTL
--  Part:       CDC351
-- 
--  Desciption: Clock driver with 3-state output
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY cdc351 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_A                   : VitalDelayType01 := VitalZeroDelay01;
        tipd_OENeg               : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_A_Y1                 : VitalDelayType01 := UnitDelay01;
        tpd_OENeg_Y1             : VitalDelayType01Z := UnitDelay01Z;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        Y1              : OUT   std_ulogic := 'U';
        Y2              : OUT   std_ulogic := 'U';
        Y3              : OUT   std_ulogic := 'U';
        Y4              : OUT   std_ulogic := 'U';
        Y5              : OUT   std_ulogic := 'U';
        Y6              : OUT   std_ulogic := 'U';
        Y7              : OUT   std_ulogic := 'U';
        Y8              : OUT   std_ulogic := 'U';
        Y9              : OUT   std_ulogic := 'U';
        Y10             : OUT   std_ulogic := 'U';
        A               : IN    std_ulogic := 'U';
        OENeg           : IN    std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of cdc351 : ENTITY IS TRUE;
END cdc351;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of cdc351 IS
    ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL A_ipd               : std_ulogic := 'U';
    SIGNAL OENeg_ipd           : std_ulogic := 'U';
    SIGNAL Y                   : std_ulogic := 'U';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (A_ipd, A, tipd_A);
        w_2 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Concurrent Procedures
    ----------------------------------------------------------------------------
    a_1: VitalIDENT (q => Y1, a => Y);
    a_2: VitalIDENT (q => Y2, a => Y);
    a_3: VitalIDENT (q => Y3, a => Y);
    a_4: VitalIDENT (q => Y4, a => Y);
    a_5: VitalIDENT (q => Y5, a => Y);
    a_6: VitalIDENT (q => Y6, a => Y);
    a_7: VitalIDENT (q => Y7, a => Y);
    a_8: VitalIDENT (q => Y8, a => Y);
    a_9: VitalIDENT (q => Y9, a => Y);
    a_10: VitalIDENT (q => Y10, a => Y);

    ----------------------------------------------------------------------------
    -- Main Behavior Process
    ----------------------------------------------------------------------------
    VitalBehavior : PROCESS (A_ipd, OENeg_ipd)

        -- Functionality Results Variables
        VARIABLE Y_zd               : std_ulogic;

        -- Output Glitch Detection Variables
        VARIABLE Y_GlitchData       : VitalGlitchDataType;

    BEGIN
        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        Y_zd := VitalBUFIF0 (data => A_ipd, enable => OENeg_ipd);

        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01Z (
            OutSignal       => Y,
            OutSignalName   => "Y",
            OutTemp         => Y_zd,
            GlitchData      => Y_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => A_ipd'LAST_EVENT,
                      PathDelay         => VitalExtendToFillDelay(tpd_A_Y1),
                      PathCondition     => TRUE),
                1 => (InputChangeTime   => OENeg_ipd'LAST_EVENT,
                      PathDelay         => tpd_OENeg_Y1,
                      PathCondition     => TRUE)
            )
        );

    END PROCESS;


END vhdl_behavioral;