cy7b991.vhd

来自「Vhdl cod for a clock for sp3e」· VHDL 代码 · 共 454 行 · 第 1/2 页

            ELSIF (FS_ipd='Z') THEN
                N := N_mid;
            ELSIF (FS_ipd='1') THEN
                N := N_high;
            END IF;
            tU <= ref_period/N;
        END IF;

    END PROCESS ADJ;

    ----------------------------------------------------------------------------
    -- PLL Process
    ----------------------------------------------------------------------------
    PLL : PROCESS (pll_out, REF_ipd, TEST_ipd)

        VARIABLE prev_pll      : time := 0 ns;

        -- Timing Check Variables
        VARIABLE Pviol_REF     : X01 := '0';
        VARIABLE PD_REF        : VitalPeriodDataType := VitalPeriodDataInit;

    BEGIN
        ------------------------------------------------------------------------
        -- Timing Check Section
        ------------------------------------------------------------------------
        IF (TimingChecksOn) THEN

            VitalPeriodPulseCheck (
                TestSignal      => pll_out,
                TestSignalName  => "PLL",
                Period          => tperiod_REF_FS_EQ_0,
                CheckEnabled    => (FS_ipd = '0'),
                HeaderMsg       => InstancePath & partID,
                PeriodData      => PD_REF,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_REF
            );

            VitalPeriodPulseCheck (
                TestSignal      => pll_out,
                TestSignalName  => "PLL",
                Period          => tperiod_REF_FS_EQ_Z,
                CheckEnabled    => (FS_ipd = 'Z'),
                HeaderMsg       => InstancePath & partID,
                PeriodData      => PD_REF,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_REF
            );

            VitalPeriodPulseCheck (
                TestSignal      => pll_out,
                TestSignalName  => "PLL",
                Period          => tperiod_REF_FS_EQ_1,
                CheckEnabled    => (FS_ipd = '1'),
                HeaderMsg       => InstancePath & partID,
                PeriodData      => PD_REF,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_REF
            );

            Violation <= Pviol_REF;

        END IF;

        IF TEST_ipd = '0' THEN
            pll_out <= TRANSPORT not pll_out AFTER pll_delay + half_per;
        ELSE
            pll_out <= REF_ipd;
        END IF;

        IF rising_edge(pll_out) THEN
            IF not vco_lock THEN
                period <= NOW - prev_pll;
            END IF;
            prev_pll := NOW;
        END IF;

    END PROCESS PLL;

    ----------------------------------------------------------------------------
    -- Q1 Process
    ----------------------------------------------------------------------------
    Q1P : PROCESS (pll_out, F1A_ipd, F1B_ipd)

    VARIABLE F1    : std_logic_vector(1 downto 0);

    BEGIN

        F1 := F1B_ipd & F1A_ipd;

        CASE F1 IS
            WHEN "00" => Q1 <= TRANSPORT pll_out AFTER (period - tU * 4);
            WHEN "0Z" => Q1 <= TRANSPORT pll_out AFTER (period - tU * 3);
            WHEN "01" => Q1 <= TRANSPORT pll_out AFTER (period - tU * 2);
            WHEN "Z0" => Q1 <= TRANSPORT pll_out AFTER (period - tU);
            WHEN "ZZ" => Q1 <= TRANSPORT pll_out AFTER period;
            WHEN "Z1" => Q1 <= TRANSPORT pll_out AFTER (period + tU);
            WHEN "10" => Q1 <= TRANSPORT pll_out AFTER (period + tU * 2);
            WHEN "1Z" => Q1 <= TRANSPORT pll_out AFTER (period + tU * 3);
            WHEN "11" => Q1 <= TRANSPORT pll_out AFTER (period + tU * 4);
            WHEN others => null;
        END CASE;

    END PROCESS Q1P;

    ----------------------------------------------------------------------------
    -- Q2 Process
    ----------------------------------------------------------------------------
    Q2P : PROCESS (pll_out, F2A_ipd, F2B_ipd)

    VARIABLE F2    : std_logic_vector(1 downto 0);

    BEGIN

        F2 := F2B_ipd & F2A_ipd;

        CASE F2 IS
            WHEN "00" => Q2 <= TRANSPORT pll_out AFTER (period - tU * 4);
            WHEN "0Z" => Q2 <= TRANSPORT pll_out AFTER (period - tU * 3);
            WHEN "01" => Q2 <= TRANSPORT pll_out AFTER (period - tU * 2);
            WHEN "Z0" => Q2 <= TRANSPORT pll_out AFTER (period - tU);
            WHEN "ZZ" => Q2 <= TRANSPORT pll_out AFTER period;
            WHEN "Z1" => Q2 <= TRANSPORT pll_out AFTER (period + tU);
            WHEN "10" => Q2 <= TRANSPORT pll_out AFTER (period + tU * 2);
            WHEN "1Z" => Q2 <= TRANSPORT pll_out AFTER (period + tU * 3);
            WHEN "11" => Q2 <= TRANSPORT pll_out AFTER (period + tU * 4);
            WHEN others => null;
        END CASE;

    END PROCESS Q2P;

    ----------------------------------------------------------------------------
    -- Q3 Process
    ----------------------------------------------------------------------------
    Q3P : PROCESS (pll_out, F3A_ipd, F3B_ipd)

    VARIABLE F3    : std_logic_vector(1 downto 0);

        -- Functionality Results Variables
        VARIABLE PrevData       : std_logic_vector(0 to 2);
        VARIABLE PrevData2      : std_logic_vector(0 to 2);
        VARIABLE PrevData4      : std_logic_vector(0 to 2);
        VARIABLE CLK_div_2      : std_ulogic := '0';
        VARIABLE CLK_div_2a     : std_ulogic := '0';
        VARIABLE CLK_div_4      : std_ulogic := '0';

    BEGIN

        F3 := F3B_ipd & F3A_ipd;

        CASE F3 IS
            WHEN "00" => 
                VitalStateTable (
                    StateTable      => TFFR_tab,
                    DataIn          => (Violation, pll_out, rst_int),
                    Result          => CLK_div_2,
                    PreviousDataIn  => PrevData
                );
                Q3 <= TRANSPORT CLK_div_2 AFTER period;
            WHEN "0Z" => Q3 <= TRANSPORT pll_out AFTER (period - tU * 6);
            WHEN "01" => Q3 <= TRANSPORT pll_out AFTER (period - tU * 4);
            WHEN "Z0" => Q3 <= TRANSPORT pll_out AFTER (period - tU * 2);
            WHEN "ZZ" => Q3 <= TRANSPORT pll_out AFTER period;
            WHEN "Z1" => Q3 <= TRANSPORT pll_out AFTER (period + tU * 2);
            WHEN "10" => Q3 <= TRANSPORT pll_out AFTER (period + tU * 4);
            WHEN "1Z" => Q3 <= TRANSPORT pll_out AFTER (period + tU * 6);
            WHEN "11" => 
                VitalStateTable (
                    StateTable      => TFFR_tab,
                    DataIn          => (Violation, pll_out, rst_int),
                    Result          => CLK_div_2a,
                    PreviousDataIn  => PrevData2
                );
                VitalStateTable (
                    StateTable      => TFFR_tab,
                    DataIn          => (Violation, CLK_div_2a, rst_int),
                    Result          => CLK_div_4,
                    PreviousDataIn  => PrevData4
                );
                Q3 <= TRANSPORT CLK_div_4 AFTER period;
            WHEN others => null;
        END CASE;

    END PROCESS Q3P;

    ----------------------------------------------------------------------------
    -- Q4 Process
    ----------------------------------------------------------------------------
    Q4P : PROCESS (pll_out, F4A_ipd, F4B_ipd)

    VARIABLE F4    : std_logic_vector(1 downto 0);

        -- Functionality Results Variables
        VARIABLE PrevData       : std_logic_vector(0 to 2);
        VARIABLE CLK_div_2      : std_ulogic := '0';

    BEGIN

        F4 := F4B_ipd & F4A_ipd;

        CASE F4 IS
            WHEN "00" => 
                VitalStateTable (
                    StateTable      => TFFR_tab,
                    DataIn          => (Violation, pll_out, rst_int),
                    Result          => CLK_div_2,
                    PreviousDataIn  => PrevData
                );
                Q4 <= TRANSPORT CLK_div_2 AFTER period;
            WHEN "0Z" => Q4 <= TRANSPORT pll_out AFTER (period - tU * 6);
            WHEN "01" => Q4 <= TRANSPORT pll_out AFTER (period - tU * 4);
            WHEN "Z0" => Q4 <= TRANSPORT pll_out AFTER (period - tU * 2);
            WHEN "ZZ" => Q4 <= TRANSPORT pll_out AFTER period;
            WHEN "Z1" => Q4 <= TRANSPORT pll_out AFTER (period + tU * 2);
            WHEN "10" => Q4 <= TRANSPORT pll_out AFTER (period + tU * 4);
            WHEN "1Z" => Q4 <= TRANSPORT pll_out AFTER (period + tU * 6);
            WHEN "11" => Q4 <= TRANSPORT not pll_out AFTER period;
            WHEN others => null;
        END CASE;

    END PROCESS Q4P;

END vhdl_behavioral;