cy7b991.vhd

来自「Vhdl cod for a clock for sp3e」· VHDL 代码 · 共 454 行 · 第 1/2 页

--------------------------------------------------------------------------------
--  File Name: cy7b991.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2000-2003 Free Model Foundry; http://www.FreeModelFoundry.com/
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0    R. Munden    00 Oct 27   Initial release
--    V1.1    R. Munden    03 Jan 29   modified use of _nwv to satisfy ncvhdl
-- 
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:    CLOCK
--  Technology: CMOS
--  Part:       CY7B991
-- 
--  Description: Programmable Skew Clock Buffer
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;
                USE FMF.ff_package.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY cy7b991 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_TEST                : VitalDelayType01 := VitalZeroDelay01;
        tipd_REF                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_FS                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_FB                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_F4B                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_F4A                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_F3B                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_F3A                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_F2B                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_F2A                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_F1B                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_F1A                 : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_REF_Q1A              : VitalDelayType := UnitDelay;
        -- tperiod_min: minimum clock period = 1/max freq
        tperiod_REF_FS_EQ_0      : VitalDelayType := UnitDelay;
        tperiod_REF_FS_EQ_Z      : VitalDelayType := UnitDelay;
        tperiod_REF_FS_EQ_1      : VitalDelayType := UnitDelay;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        -- 'Z' denotes internal MID state of peculiar three-state
        -- input used by this part
        TEST            : IN    std_ulogic := 'Z';
        REF             : IN    std_ulogic := 'U';
        FS              : IN    std_ulogic := 'Z';
        FB              : IN    std_ulogic := 'U';
        Q4B             : OUT   std_ulogic := 'U';
        Q4A             : OUT   std_ulogic := 'U';
        F4B             : IN    std_ulogic := 'Z';
        F4A             : IN    std_ulogic := 'Z';
        Q3B             : OUT   std_ulogic := 'U';
        Q3A             : OUT   std_ulogic := 'U';
        F3B             : IN    std_ulogic := 'Z';
        F3A             : IN    std_ulogic := 'Z';
        Q2B             : OUT   std_ulogic := 'U';
        Q2A             : OUT   std_ulogic := 'U';
        F2B             : IN    std_ulogic := 'Z';
        F2A             : IN    std_ulogic := 'Z';
        Q1B             : OUT   std_ulogic := 'U';
        Q1A             : OUT   std_ulogic := 'U';
        F1B             : IN    std_ulogic := 'Z';
        F1A             : IN    std_ulogic := 'Z'
    );
    ATTRIBUTE VITAL_LEVEL0 of cy7b991 : ENTITY IS TRUE;
END cy7b991;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of cy7b991 IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT partID            : STRING := "CY7B991";

    SIGNAL TEST_ipd            : std_ulogic := 'Z';
    SIGNAL REF_ipd             : std_ulogic := 'U';
    SIGNAL FS_ipd              : std_ulogic := 'Z';
    SIGNAL FB_ipd              : std_ulogic := 'U';
    SIGNAL F4B_ipd             : std_ulogic := 'Z';
    SIGNAL F4A_ipd             : std_ulogic := 'Z';
    SIGNAL F3B_ipd             : std_ulogic := 'Z';
    SIGNAL F3A_ipd             : std_ulogic := 'Z';
    SIGNAL F2B_ipd             : std_ulogic := 'Z';
    SIGNAL F2A_ipd             : std_ulogic := 'Z';
    SIGNAL F1B_ipd             : std_ulogic := 'Z';
    SIGNAL F1A_ipd             : std_ulogic := 'Z';
    SIGNAL Q1                  : std_ulogic := 'Z';
    SIGNAL Q2                  : std_ulogic := 'Z';
    SIGNAL Q3                  : std_ulogic := 'Z';
    SIGNAL Q4                  : std_ulogic := 'Z';
    SIGNAL FB_nwv              : UX01;
    SIGNAL pll_out             : std_logic := '1';
    SIGNAL rst_int             : std_ulogic := '1';
    SIGNAL vco_lock            : boolean;
    SIGNAL pll_delay           : time := 0 ns;
    SIGNAL half_per            : time := 6 ns;
    SIGNAL period              : time := 0 ns;
    SIGNAL tU                  : time := 0 ns;
    SIGNAL Violation           : X01 := '0';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (TEST_ipd, TEST, tipd_TEST);
        w_2 : VitalWireDelay (REF_ipd, REF, tipd_REF);
        w_3 : VitalWireDelay (FS_ipd, FS, tipd_FS);
        w_4 : VitalWireDelay (FB_ipd, FB, tipd_FB);
        w_7 : VitalWireDelay (F4B_ipd, F4B, tipd_F4B);
        w_8 : VitalWireDelay (F4A_ipd, F4A, tipd_F4A);
        w_11 : VitalWireDelay (F3B_ipd, F3B, tipd_F3B);
        w_12 : VitalWireDelay (F3A_ipd, F3A, tipd_F3A);
        w_15 : VitalWireDelay (F2B_ipd, F2B, tipd_F2B);
        w_16 : VitalWireDelay (F2A_ipd, F2A, tipd_F2A);
        w_19 : VitalWireDelay (F1B_ipd, F1B, tipd_F1B);
        w_20 : VitalWireDelay (F1A_ipd, F1A, tipd_F1A);

    END BLOCK;

    FB_nwv <= to_UX01(FB_ipd);
    Q1A <= Q1;
    Q1B <= Q1;
    Q2A <= Q2;
    Q2B <= Q2;
    Q3A <= Q3;
    Q3B <= Q3;
    Q4A <= Q4;
    Q4B <= Q4;

    ----------------------------------------------------------------------------
    -- ADJ Process
    ----------------------------------------------------------------------------
    ADJ : PROCESS (FB_nwv, REF_ipd, FS_ipd, vco_lock)

        CONSTANT N_low       : integer :=44;
        CONSTANT N_mid       : integer :=26;
        CONSTANT N_high      : integer :=16;

        VARIABLE vlck        : std_ulogic := '0';
        VARIABLE fb_period   : time := 0 ns;
        VARIABLE ref_period  : time := 0 ns;
        VARIABLE prev_ref    : time := 0 ns;
        VARIABLE prev_fb     : time := 0 ns;
        VARIABLE toggle1     : boolean;
        VARIABLE toggle2     : boolean;
        VARIABLE N           : integer;

    BEGIN

        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        IF rising_edge(REF_ipd) THEN
            ref_period := NOW - prev_ref;
            prev_ref := NOW;
            IF FB_nwv = 'X' THEN
               rst_int <= '1', '0' AFTER 5 ns;
            END IF;
        END IF;

        IF (FB_nwv'event AND FB_nwv = '0') THEN
            rst_int <= '0';
            fb_period := NOW - prev_fb;
            prev_fb := NOW;

            IF toggle1 AND not(toggle2) THEN
                IF fb_period > ref_period THEN
                    half_per <= half_per - 50 ps;
                    vco_lock <= false;
                    vlck := '0';
                ELSIF fb_period < ref_period THEN
                    half_per <= half_per + 60 ps;
                    vco_lock <= false;
                    vlck := '0';
                ELSE
                    vco_lock <= true;
                    vlck := '1';
                END IF;
            END IF;
            toggle1 := not toggle1;
            IF toggle1 THEN
                toggle2 := not toggle2;
            ELSE
                pll_delay <= 0 ps;
            END IF;
        END IF;


        IF rising_edge(FB_ipd) AND vco_lock AND toggle1 AND toggle2 THEN
            IF (prev_ref + tpd_REF_Q1A) < NOW THEN
                IF pll_delay < ref_period THEN
                    pll_delay <= pll_delay - 200 ps;
                END IF;
            END IF;
        END IF;

        IF (vco_lock AND vco_lock'EVENT) OR FS_ipd'EVENT THEN
            IF (FS_ipd='0') THEN
                N := N_low;