clk2510.vhd

来自「Vhdl cod for a clock for sp3e」· VHDL 代码 · 共 266 行

--------------------------------------------------------------------------------
--  File Name: clk2510.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2002 Free Model Foundry; http://www.FreeModelFoundry.com/
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0    R. Munden    02 Dec 26   Initial release
-- 
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:    CLOCK
--  Technology:  
--  Part:       CLK2510
-- 
--  Description: Phase-Lock Loop Clock Driver w/ 3-State Outputs
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY clk2510 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_G                   : VitalDelayType01 := VitalZeroDelay01;
        tipd_CLK                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_FBIN                : VitalDelayType01 := VitalZeroDelay01;
        tipd_AVCC                : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_G_Y0                 : VitalDelayType01Z := UnitDelay01Z;
        tpd_CLK_Y0               : VitalDelayType01 := UnitDelay01;
        -- tperiod_min: minimum clock period = 1/max freq
        tperiod_FBIN_posedge     : VitalDelayType := UnitDelay;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        Y0              : OUT   std_ulogic := 'U';
        Y1              : OUT   std_ulogic := 'U';
        Y2              : OUT   std_ulogic := 'U';
        Y3              : OUT   std_ulogic := 'U';
        Y4              : OUT   std_ulogic := 'U';
        Y5              : OUT   std_ulogic := 'U';
        Y6              : OUT   std_ulogic := 'U';
        Y7              : OUT   std_ulogic := 'U';
        Y8              : OUT   std_ulogic := 'U';
        Y9              : OUT   std_ulogic := 'U';
        FBOUT           : OUT   std_ulogic := 'U';
        AVCC            : IN    std_ulogic := 'U';
        G               : IN    std_ulogic := 'U';
        CLK             : IN    std_ulogic := 'U';
        FBIN            : IN    std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of clk2510 : ENTITY IS TRUE;
END clk2510;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of clk2510 IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL G_ipd               : std_ulogic := 'U';
    SIGNAL CLK_ipd             : std_ulogic := 'U';
    SIGNAL FBIN_ipd            : std_ulogic := 'U';
    SIGNAL AVCC_ipd            : std_ulogic := 'U';
    SIGNAL pll_out             : std_ulogic := '1';
    SIGNAL rst_int             : std_ulogic := '0';
    SIGNAL vco_lock            : boolean;
    SIGNAL pll_delay           : time := 0 ns;
    SIGNAL half_per            : time := 6 ns;
    SIGNAL Y                   : std_ulogic := 'U';
    SIGNAL Violation           : X01 := '0';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_14 : VitalWireDelay (G_ipd, G, tipd_G);
        w_15 : VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
        w_16 : VitalWireDelay (FBIN_ipd, FBIN, tipd_FBIN);
        w_17 : VitalWireDelay (AVCC_ipd, AVCC, tipd_AVCC);

    END BLOCK;

    Y0 <= Y;
    Y1 <= Y;
    Y2 <= Y;
    Y3 <= Y;
    Y4 <= Y;
    Y5 <= Y;
    Y6 <= Y;
    Y7 <= Y;
    Y8 <= Y;
    Y9 <= Y;

    ----------------------------------------------------------------------------
    -- ADJ Process
    ----------------------------------------------------------------------------
    ADJ : PROCESS (FBIN_ipd, CLK_ipd)

        VARIABLE fbi_period   : time := 0 ns;
        VARIABLE clk_period   : time := 0 ns;
        VARIABLE prev_clk     : time := 0 ns;
        VARIABLE prev_fbi     : time := 0 ns;
        VARIABLE toggle1      : boolean;
        VARIABLE toggle2      : boolean;

        -- Timing Check Variables
        VARIABLE Pviol_FBIN     : X01 := '0';
        VARIABLE PD_FBIN        : VitalPeriodDataType := VitalPeriodDataInit;

    BEGIN
        ------------------------------------------------------------------------
        -- Timing Check Section
        ------------------------------------------------------------------------
        IF (TimingChecksOn) THEN

            VitalPeriodPulseCheck (
                TestSignal      => FBIN_ipd,
                TestSignalName  => "FBIN_ipd",
                Period          => tperiod_FBIN_posedge,
                CheckEnabled    => TRUE,
                HeaderMsg       => InstancePath & "/clk2510",
                PeriodData      => PD_FBIN,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_FBIN
            );

        END IF;

        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        Violation <= Pviol_FBIN;

        IF rising_edge(CLK_ipd) THEN
            clk_period := NOW - prev_clk;
            prev_clk := NOW;
            IF FBIN_ipd = 'X' THEN
               rst_int <= '1', '0' AFTER 5 ns;
            END IF;
        END IF;

        IF (FBIN_ipd'event AND FBIN_ipd = '0') THEN
            rst_int <= '0';
            fbi_period := NOW - prev_fbi;
            prev_fbi := NOW;

            IF toggle1 AND toggle2 THEN
                IF fbi_period > clk_period THEN
                    half_per <= half_per - 50 ps;
                    vco_lock <= false;
                ELSIF fbi_period < clk_period THEN
                    half_per <= half_per + 60 ps;
                    vco_lock <= false;
                ELSE
                    vco_lock <= true;
                END IF;
            END IF;
            toggle1 := not toggle1;
            IF toggle1 THEN
                toggle2 := not toggle2;
            ELSE
                pll_delay <= 0 ps;
            END IF;
        END IF;

        IF rising_edge(FBIN_ipd) AND vco_lock AND toggle1 AND toggle2 THEN
            IF (prev_clk + 150 ps) < NOW THEN
                IF pll_delay < clk_period THEN
                    pll_delay <= 30 ps;
                END IF;
            END IF;
        END IF;

    END PROCESS ADJ;

    ----------------------------------------------------------------------------
    -- PLL Process
    ----------------------------------------------------------------------------
    PLL : PROCESS (pll_out, CLK_ipd, G_ipd, AVCC_ipd)

        -- Functionality Results Variables
        VARIABLE Y_zd              : std_ulogic;
        VARIABLE F_zd              : std_ulogic;

        -- Output Glitch Detection Variables
        VARIABLE Y_GlitchData      : VitalGlitchDataType;
        VARIABLE F_GlitchData      : VitalGlitchDataType;

    BEGIN

        IF AVCC_ipd = '1' THEN
            pll_out <= TRANSPORT not pll_out AFTER pll_delay + half_per;
        ELSE
            pll_out <= CLK_ipd;
        END IF;
        Y_zd := VitalBUFIF1 (data => pll_out, enable => G_ipd);
        F_zd := pll_out;

        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01 (
            OutSignal       => FBOUT,
            OutSignalName   => "FBOUT",
            OutTemp         => F_zd,
            GlitchData      => F_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => pll_out'LAST_EVENT,
                      PathDelay         => VitalZeroDelay01,
                      PathCondition     => AVCC_ipd = '1'),
                1 => (InputChangeTime   => pll_out'LAST_EVENT,
                      PathDelay         => tpd_CLK_Y0,
                      PathCondition     => AVCC_ipd /= '1')
            )
        );

        VitalPathDelay01Z (
            OutSignal       => Y,
            OutSignalName   => "Y",
            OutTemp         => Y_zd,
            GlitchData      => Y_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => pll_out'LAST_EVENT,
                      PathDelay         => VitalZeroDelay01Z,
                      PathCondition     => AVCC_ipd = '1'),
                1 => (InputChangeTime   => pll_out'LAST_EVENT,
                      PathDelay         => VitalExtendtoFillDelay(tpd_CLK_Y0),
                      PathCondition     => AVCC_ipd /= '1'),
                2 => (InputChangeTime   => G_ipd'LAST_EVENT,
                      PathDelay         => tpd_G_Y0,
                      PathCondition     => TRUE)
            )
        );

    END PROCESS PLL;

END vhdl_behavioral;