mpc940.vhd

来自「Vhdl cod for a clock for sp3e」· VHDL 代码 · 共 184 行

--------------------------------------------------------------------------------
--  File Name: mpc940.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1999 Free Model Foundry http://www.FreeModelFoundry.com/
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0    R. Munden    99 JUN 09   Initial release
-- 
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:    Clock
--  Technology: LVCMOS
--  Part:       MPC940
-- 
--  Description: 1:18 Clock Distributor with Muxed Inputs
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY mpc940 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_LVCMOSCLK           : VitalDelayType01 := VitalZeroDelay01;
        tipd_PECLCLK             : VitalDelayType01 := VitalZeroDelay01;
        tipd_CLKSEL              : VitalDelayType01 := VitalZeroDelay01;
        tipd_PECLCLKNeg          : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_LVCMOSCLK_Q0         : VitalDelayType01 := UnitDelay01;
        tpd_PECLCLK_Q0           : VitalDelayType01 := UnitDelay01;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        MsgOn               : BOOLEAN := DefaultMsgOn;
        XOn                 : Boolean := DefaultXOn;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        Q17             : OUT   std_logic := 'U';
        Q16             : OUT   std_logic := 'U';
        Q15             : OUT   std_logic := 'U';
        Q14             : OUT   std_logic := 'U';
        Q13             : OUT   std_logic := 'U';
        Q12             : OUT   std_logic := 'U';
        Q11             : OUT   std_logic := 'U';
        Q10             : OUT   std_logic := 'U';
        Q9              : OUT   std_logic := 'U';
        Q8              : OUT   std_logic := 'U';
        Q7              : OUT   std_logic := 'U';
        Q6              : OUT   std_logic := 'U';
        Q5              : OUT   std_logic := 'U';
        Q4              : OUT   std_logic := 'U';
        Q3              : OUT   std_logic := 'U';
        Q2              : OUT   std_logic := 'U';
        Q1              : OUT   std_logic := 'U';
        Q0              : OUT   std_logic := 'U';
        LVCMOSCLK       : IN    std_logic := 'L';
        PECLCLK         : IN    std_logic := 'L';
        CLKSEL          : IN    std_logic := 'L';
        PECLCLKNeg      : IN    std_logic := 'H'
    );
    ATTRIBUTE VITAL_LEVEL0 of mpc940 : ENTITY IS TRUE;
END mpc940;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of mpc940 IS
    ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL LVCMOSCLK_ipd       : std_ulogic := 'X';
    SIGNAL PECLCLK_ipd         : std_ulogic := 'X';
    SIGNAL CLKSEL_ipd          : std_ulogic := 'X';
    SIGNAL PECLCLKNeg_ipd      : std_ulogic := 'X';
    SIGNAL Qint                : std_ulogic := 'X';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_19 : VitalWireDelay (LVCMOSCLK_ipd, LVCMOSCLK, tipd_LVCMOSCLK);
        w_20 : VitalWireDelay (PECLCLK_ipd, PECLCLK, tipd_PECLCLK);
        w_21 : VitalWireDelay (CLKSEL_ipd, CLKSEL, tipd_CLKSEL);
        w_22 : VitalWireDelay (PECLCLKNeg_ipd, PECLCLKNeg, tipd_PECLCLKNeg);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Concurrent procedure calls
    ----------------------------------------------------------------------------
    a_1: VITALBUF (q => Q0, a => Qint);
    a_2: VITALBUF (q => Q1, a => Qint);
    a_3: VITALBUF (q => Q2, a => Qint);
    a_4: VITALBUF (q => Q3, a => Qint);
    a_5: VITALBUF (q => Q4, a => Qint);
    a_6: VITALBUF (q => Q5, a => Qint);
    a_7: VITALBUF (q => Q6, a => Qint);
    a_8: VITALBUF (q => Q7, a => Qint);
    a_9: VITALBUF (q => Q8, a => Qint);
    a_10: VITALBUF (q => Q9, a => Qint);
    a_11: VITALBUF (q => Q10, a => Qint);
    a_12: VITALBUF (q => Q11, a => Qint);
    a_13: VITALBUF (q => Q12, a => Qint);
    a_14: VITALBUF (q => Q13, a => Qint);
    a_15: VITALBUF (q => Q14, a => Qint);
    a_16: VITALBUF (q => Q15, a => Qint);
    a_17: VITALBUF (q => Q16, a => Qint);
    a_18: VITALBUF (q => Q17, a => Qint);

    ----------------------------------------------------------------------------
    -- CLock Process with mux
    ----------------------------------------------------------------------------
    ECLClock_mux : PROCESS (PECLCLK_ipd, PECLCLKNeg_ipd, LVCMOSCLK_ipd,
                            CLKSEL_ipd)

        -- Functionality Results Variables
        VARIABLE Mode           : X01;
        VARIABLE CLK_var        : std_ulogic;
        VARIABLE Q_zd           : std_ulogic;
        VARIABLE PrevData       : std_logic_vector(0 to 1);

        -- Output Glitch Detection Variables
        VARIABLE CLK_GlitchData : VitalGlitchDataType;

    BEGIN

        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        VitalStateTable (
            StateTable      => diff_rec_tab,
            DataIn          => (PECLCLK_ipd, PECLCLKNeg_ipd),
            Result          => CLK_var,
            PreviousDataIn  => PrevData
        );

        Q_zd := VitalMUX2 (
                   data0   => CLK_var,
                   data1   => LVCMOSCLK_ipd,
                   dselect => CLKSEL_ipd
                );

        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01 (
            OutSignal       => Qint,
            OutSignalName   => "Q",
            OutTemp         => Q_zd,
            GlitchData      => CLK_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => PECLCLK_ipd'LAST_EVENT,
                      PathDelay         => tpd_PECLCLK_Q0,
                      PathCondition     => (CLKSEL_ipd = '0' OR
                                            CLKSEL_ipd = 'L')),
                1 => (InputChangeTime   => LVCMOSCLK_ipd'LAST_EVENT,
                      PathDelay         => tpd_LVCMOSCLK_Q0,
                      PathCondition     => (CLKSEL_ipd /= '0' OR
                                            CLKSEL_ipd /= 'L'))
            )
        );

    END PROCESS;

END vhdl_behavioral;