cy2313anz.vhd
来自「Vhdl cod for a clock for sp3e」· VHDL 代码 · 共 552 行 · 第 1/2 页
VHD
552 行
---------------------------------------------------------------------------------- File Name: cy2313anz.vhd---------------------------------------------------------------------------------- Copyright (C) 1999-2002 Free Model Foundry; http://www.FreeModelFoundry.com/-- -- This program is free software; you can redistribute it and/or modify-- it under the terms of the GNU General Public License version 2 as-- published by the Free Software Foundation.-- -- MODIFICATION HISTORY:-- -- version: | author: | mod date: | changes made:-- V1.0 R. Munden 99 JAN 13 Initial release-- V1.1 R. Munden 00 JUL 24 corrected path delay conditions for I2C-- V1.2 R. Munden 02 MAR 29 corrected for ModelSim 5.6-- ---------------------------------------------------------------------------------- PART DESCRIPTION:-- -- Library: CLOCK-- Technology: LVTTL-- Part: CY2313ANZ-- -- Description: Clock Buffer with I2C--------------------------------------------------------------------------------LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL;LIBRARY FMF; USE FMF.gen_utils.ALL;---------------------------------------------------------------------------------- ENTITY DECLARATION--------------------------------------------------------------------------------ENTITY cy2313anz IS GENERIC ( -- tipd delays: interconnect path delays tipd_BUFIN : VitalDelayType01 := VitalZeroDelay01; tipd_SDATA : VitalDelayType01 := VitalZeroDelay01; tipd_SCLK : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_BUFIN_SDR0 : VitalDelayType01 := UnitDelay01; tpd_SCLK_SDR0 : VitalDelayType01Z := UnitDelay01Z; tpd_SCLK_SDATA : VitalDelayType01Z := UnitDelay01Z; -- tsetup values: setup times tsetup_SDATA_SCLK : VitalDelayType := UnitDelay; -- thold values: hold times thold_SDATA_SCLK : VitalDelayType := UnitDelay; -- tpw values: pulse widths tpw_BUFIN_posedge : VitalDelayType := UnitDelay; tpw_BUFIN_negedge : VitalDelayType := UnitDelay; tpw_SCLK_posedge : VitalDelayType := UnitDelay; tpw_SCLK_negedge : VitalDelayType := UnitDelay; -- tperiod_min: minimum clock period = 1/max freq tperiod_BUFIN_posedge : VitalDelayType := UnitDelay; tperiod_SCLK_posedge : VitalDelayType := UnitDelay; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( BUFIN : IN std_ulogic := 'U'; SDATA : INOUT std_ulogic := 'H'; SCLK : IN std_ulogic := 'H'; SDR0 : OUT std_ulogic := 'U'; SDR1 : OUT std_ulogic := 'U'; SDR2 : OUT std_ulogic := 'U'; SDR3 : OUT std_ulogic := 'U'; SDR4 : OUT std_ulogic := 'U'; SDR5 : OUT std_ulogic := 'U'; SDR6 : OUT std_ulogic := 'U'; SDR7 : OUT std_ulogic := 'U'; SDR8 : OUT std_ulogic := 'U'; SDR9 : OUT std_ulogic := 'U'; SDR10 : OUT std_ulogic := 'U'; SDR11 : OUT std_ulogic := 'U'; SDR12 : OUT std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of cy2313anz : ENTITY IS TRUE;END cy2313anz;---------------------------------------------------------------------------------- ARCHITECTURE DECLARATION--------------------------------------------------------------------------------ARCHITECTURE vhdl_behavioral of cy2313anz IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL BUFIN_ipd : std_ulogic := 'X'; SIGNAL SDATA_ipd : std_ulogic := 'X'; SIGNAL SCLK_ipd : std_ulogic := 'X'; SIGNAL Byte0 : std_logic_vector(7 downto 0) := (OTHERS => '1'); SIGNAL Byte1 : std_logic_vector(7 downto 0) := (OTHERS => '1'); SIGNAL Byte2 : std_logic_vector(7 downto 0) := (OTHERS => '1'); CONSTANT Address : std_logic_vector(7 downto 0) := "01001011"; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (BUFIN_ipd, BUFIN, tipd_BUFIN); w_2 : VitalWireDelay (SDATA_ipd, SDATA, tipd_SDATA); w_3 : VitalWireDelay (SCLK_ipd, SCLK, tipd_SCLK); END BLOCK; ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VitalBehavior1 : PROCESS (BUFIN_ipd, Byte0, Byte1, Byte2) -- Timing Check Variables VARIABLE Pviol_BUFIN : X01 := '0'; VARIABLE PD_BUFIN : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; -- Functionality Results Variables VARIABLE SDR0_zd : std_ulogic; VARIABLE SDR1_zd : std_ulogic; VARIABLE SDR2_zd : std_ulogic; VARIABLE SDR3_zd : std_ulogic; VARIABLE SDR4_zd : std_ulogic; VARIABLE SDR5_zd : std_ulogic; VARIABLE SDR6_zd : std_ulogic; VARIABLE SDR7_zd : std_ulogic; VARIABLE SDR8_zd : std_ulogic; VARIABLE SDR9_zd : std_ulogic; VARIABLE SDR10_zd : std_ulogic; VARIABLE SDR11_zd : std_ulogic; VARIABLE SDR12_zd : std_ulogic; -- Output Glitch Detection Variables VARIABLE SDR0_GlitchData : VitalGlitchDataType; VARIABLE SDR1_GlitchData : VitalGlitchDataType; VARIABLE SDR2_GlitchData : VitalGlitchDataType; VARIABLE SDR3_GlitchData : VitalGlitchDataType; VARIABLE SDR4_GlitchData : VitalGlitchDataType; VARIABLE SDR5_GlitchData : VitalGlitchDataType; VARIABLE SDR6_GlitchData : VitalGlitchDataType; VARIABLE SDR7_GlitchData : VitalGlitchDataType; VARIABLE SDR8_GlitchData : VitalGlitchDataType; VARIABLE SDR9_GlitchData : VitalGlitchDataType; VARIABLE SDR10_GlitchData : VitalGlitchDataType; VARIABLE SDR11_GlitchData : VitalGlitchDataType; VARIABLE SDR12_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalPeriodPulseCheck ( TestSignal => BUFIN_ipd, TestSignalName => "BUFIN_ipd", Period => tperiod_BUFIN_posedge, PulseWidthHigh => tpw_BUFIN_posedge, PulseWidthLow => tpw_BUFIN_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & "/cy2313anz", PeriodData => PD_BUFIN, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_BUFIN ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Pviol_BUFIN; IF (Violation = '0') THEN SDR0_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte0(0) ); SDR1_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte0(1) ); SDR2_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte0(2) ); SDR3_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte0(3) ); SDR4_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte0(6) ); SDR5_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte0(7) ); SDR6_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte1(0) ); SDR7_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte1(1) ); SDR8_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte1(4) ); SDR9_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte1(5) ); SDR10_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte1(6) ); SDR11_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte1(7) ); SDR12_zd := VitalBUFIF1 (data => BUFIN_ipd, enable => Byte2(6) ); END IF; ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01Z ( OutSignal => SDR0, OutSignalName => "SDR0", OutTemp => SDR0_zd, Paths => ( 0 => (InputChangeTime => BUFIN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_BUFIN_SDR0), PathCondition => (Byte0(0) = '1')), 1 => (InputChangeTime => Byte0(0)'LAST_EVENT, PathDelay => tpd_SCLK_SDR0, PathCondition => TRUE ) ), GlitchData => SDR0_GlitchData ); VitalPathDelay01Z ( OutSignal => SDR1, OutSignalName => "SDR1", OutTemp => SDR1_zd, Paths => ( 0 => (InputChangeTime => BUFIN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_BUFIN_SDR0), PathCondition => (Byte0(1) = '1')), 1 => (InputChangeTime => Byte0(1)'LAST_EVENT, PathDelay => tpd_SCLK_SDR0, PathCondition => TRUE ) ), GlitchData => SDR1_GlitchData ); VitalPathDelay01Z ( OutSignal => SDR2, OutSignalName => "SDR2", OutTemp => SDR2_zd, Paths => ( 0 => (InputChangeTime => BUFIN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_BUFIN_SDR0), PathCondition => (Byte0(2) = '1')), 1 => (InputChangeTime => Byte0(2)'LAST_EVENT, PathDelay => tpd_SCLK_SDR0, PathCondition => TRUE ) ), GlitchData => SDR2_GlitchData ); VitalPathDelay01Z ( OutSignal => SDR3, OutSignalName => "SDR3", OutTemp => SDR3_zd, Paths => ( 0 => (InputChangeTime => BUFIN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_BUFIN_SDR0), PathCondition => (Byte0(3) = '1')), 1 => (InputChangeTime => Byte0(3)'LAST_EVENT, PathDelay => tpd_SCLK_SDR0, PathCondition => TRUE ) ), GlitchData => SDR3_GlitchData ); VitalPathDelay01Z ( OutSignal => SDR4, OutSignalName => "SDR4", OutTemp => SDR4_zd, Paths => ( 0 => (InputChangeTime => BUFIN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_BUFIN_SDR0), PathCondition => (Byte0(6) = '1')), 1 => (InputChangeTime => Byte0(6)'LAST_EVENT, PathDelay => tpd_SCLK_SDR0, PathCondition => TRUE ) ), GlitchData => SDR4_GlitchData ); VitalPathDelay01Z ( OutSignal => SDR5, OutSignalName => "SDR5", OutTemp => SDR5_zd, Paths => ( 0 => (InputChangeTime => BUFIN_ipd'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_BUFIN_SDR0), PathCondition => (Byte0(7) = '1')), 1 => (InputChangeTime => Byte0(7)'LAST_EVENT, PathDelay => tpd_SCLK_SDR0, PathCondition => TRUE ) ),⌨️ 快捷键说明
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